參數(shù)資料
型號： AD9980KSTZ-80
廠商： ANALOG DEVICES INC
元件分類： 其它接口
英文描述： High Performance 8-Bit Display Interface
中文描述： SPECIALTY INTERFACE CIRCUIT, PQFP80
封裝： LEAD FREE, MS-026BEC, LQFP-80
文件頁數(shù)： 22/44頁
文件大?。?/td> 507K
代理商： AD9980KSTZ-80
AD9980
Preliminary Technical Data
TWO-WIRE SERIAL REGISTER MAP
The AD9980 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to
write and read the control registers through the two-wire serial interface port.
Table 12. Control Register Map
Read and
Write or
Read Only
Bits
Value
Name
0x00
RO
7:0
Chip Revision
0x01
R/W
7:0
0110 1001
PLL Div MSB
Rev. 0 | Page 22 of 44
Hexadecimal
Address
Default
Register
Description
An 8-bit register that represents the silicon revision level.
This register is for Bits [11:4] of the PLL divider. Larger values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. (This will give the PLL more time to
lock).
1
Bits [7:4] LSBs of the PLL divider word. Links to the PLL Div MSB to
make a 12-bit register.
1
Bits [7:6] VCO Range. Selects VCO frequency range.
(See PLL description).
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description).
Bit 2. External Clock Enable
ADC clock phase adjustment. Larger values mean more delay.
(1 LSB = T/32).
7-Bit Red Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.
2
Must be written to 0x00 following a write of Register 0x05 for
proper operation.
7-Bit Green Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.
2
Must be written to 0x00 following a write of Register 0x07 for
proper operation.
7-Bit Blue Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.
2
Must be written to 0x00 following a write of Register 0x09 for
proper operation.
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.
1
Linked with 0x0B to form the 9-bit red offset that controls the dc
offset (brightness) of the red channel in auto-offset mode.
8-Bit MSB of the Green Channel Offset Control. Controls the dc
offset (brightness) of each respective channel. Bigger values
decrease brightness.
1
Linked with 0x0D to form the 9-bit green offset that controls the
dc offset (brightness) of the green channel in auto-offset mode.
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.
1
Linked with 0x0F to form the 9-bit blue offset that controls the dc
offset (brightness) of the blue channel in auto-offset mode.
This register sets the threshold of the sync separator’s digital
comparator.
0x02
R/W
7:4
1101 ****
PLL Div LSB
0x03
R/W
7:6
01** ****
VCO/CPMP
5:3
**00 1***
0x04
R/W
2
7:3
**** *0**
1000 0***
Phase Adjust
0x05
R/W
6:0
*100 0000
Red Gain MSB
0x06
R/W
7:0
0000 0000
0x07
R/W
6:0
*100 0000
Green Gain
MSB
0x08
R/W
7:0
0000 0000
0x09
R/W
6:0
*100 0000
Blue Gain MSB
0x0A
R/W
7:0
0000 0000
0x0B
R/W
7:0
0100 0000
Red Offset MSB
0x0C
R/W
7
0*** ****
Red Offset
0x0D
R/W
7:0
0100 0000
Green Offset
MSB
0x0E
R/W
7
0*** ****
Green Offset
0x0F
R/W
7:0
0100 0000
Blue Offset
MSB
0x10
R/W
7
0*** ****
Blue Offset
0x11
R/W
7:0
0010 0000
Sync Separator
Threshold
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9980KSTZ-95 功能描述:IC INTERFACE 8BIT ANALOG 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD9980KSTZ-RL95 制造商:Analog Devices 功能描述:
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AD9981 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 10-Bit Display Interface
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