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| 型號： | AD9958/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9958 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186) AD9958/59 Eval Brd Schematics AD9958/59 Eval Brd Gerber Files AD9958 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9958 |
| 主要屬性： | 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 500MHz 2 通道圖形用戶界面 |
| 已供物品： | 板，線纜，軟件 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD9958BCPZ-REEL7-ND - IC DDS DUAL 10BIT DAC 56LFCSP AD9958BCPZ-ND - IC DDS DUAL 500MSPS DAC 56LFCSP |
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AD9958
Data Sheet
Rev. B | Page 10 of 44
Pin No.
Mnemonic
I/O1
Description
24
CLK_MODE_SEL
I
Control Pin for the Oscillator Section. Caution: Do not drive this pin beyond 1.8 V.
When high (1.8 V), the oscillator section is enabled to accept a crystal as the
REF_CLK source. When low, the oscillator section is bypassed.
27
LOOP_FILTER
I
Connects to the external zero compensation network of the PLL loop filter.
Typically, the network consists of a 0 resistor in series with a 680 pF capacitor
tied to AVDD.
28, 32, 34, 38
NC
N/A
No Connection.
40, 41, 42, 43
P0, P1, P2, P3
I
Data pins used for modulation (FSK, PSK, ASK), to start/stop for the sweep
accumulators, or used to ramp up/ramp down the output amplitude. The data is
synchronous to the SYNC_CLK (Pin 54). The data inputs must meet the setup and
hold time requirements to the SYNC_CLK. The functionality of these pins is
controlled by profile pin configuration (PPC) bits (FR1[14:12]).
46
I/O_UPDATE
I
A rising edge transfers data from the serial I/O port buffer to active registers.
I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the
setup and hold time requirements to the SYNC_CLK to guarantee a fixed pipeline
delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of pipeline
uncertainty exists. The minimum pulse width is one SYNC_CLK period.
47
CS
I
Active Low Chip Select. Allows multiple devices to share a common I/O bus (SPI).
48
SCLK
I
Serial Data Clock for I/O Operations. Data bits are written on the rising edge of
SCLK and read on the falling edge of SCLK.
49
DVDD_I/O
I
3.3 V Digital Power Supply for SPI Port and Digital I/O.
50
SDIO_0
I/O
Data Pin SDIO_0 is dedicated to the serial port I/O only.
51, 52, 53
SDIO_1, SDIO_2,
SDIO_3
I/O
Data Pin SDIO_1, Data Pin SDIO_2, and Data Pin SDIO_3 can be used for the serial
I/O port or used to initiate a ramp-up/ramp-down (RU/RD) of the DAC output
amplitude.
54
SYNC_CLK
O
The SYNC_CLK runs at one fourth the system clock rate. It can be disabled. I/O_UPDATE
or data (Pin 40 to Pin 43) is synchronous to the SYNC_CLK. To guarantee a fixed
pipeline delay of data to DAC output, I/O_UPDATE or data (Pin 40 to Pin 43) must
meet the setup and hold time requirements to the rising edge of SYNC_CLK;
otherwise, a ±1 SYNC_CLK period of uncertainty exists.
1
I = input, O = output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs |
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD9959_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
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