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參數(shù)資料
| 型號： | AD9957BSVZREEL13 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QFP48 |
| 封裝： | PLASTIC, MS-026-AED-HD, TQFP-48 |
| 文件頁數(shù)： | 35/38頁 |
| 文件大?。?/td> | 602K |
| 代理商： | AD9957BSVZREEL13 |
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PRELIMINARY TECHNICAL DATA
AD9957
Rev. PrF | Page 35 of 38
When
CFR2<7>
= 0
(default)
, the Frequency Tuning Word,
Phase Offset and Amplitude Scalar pipe delays are mini-
mized. The output will reflect amplitude changes before it
reflects phase changes, and phase changes before it reflects
frequency changes.
When
CFR2<7>
= 1, the Frequency Tuning Word, Phase
Offset and Amplitude Scalar pipe delays are implemented
such that the simultaneous application of changes in fre-
quency, phase and amplitude are reflected on the output si-
multaneously too.
CFR2<6>
:
Data Assembler Holds Last Value bit
When
CFR2<6>
= 0
(default)
, the data port drives logic ze-
ros onto the signal processing data path when transmission
is disabled.
When
CFR2<6>
= 1, the data port holds the last data word
registered when transmission is disabled.
CFR2<5>
:
Sync Sample Error Mask bit
CFR2<5>
= 0 disables the SYNC_SMP_ERR pin.
CFR2<5>
= 1
(default)
enables the SYNC_SMP_ERR pin.
CFR2<3:0>
:
FM Gain bits
.
When
operating the device in single tone mode and FM
modulation is selected via the Data Port Destination bits, if
the Single Tone Data Port Enable bit is set, these bits are
used to select one of 16 possible 16-bit ranges relative to the
32-bit DDS tuning word
.
Control Function Register #3 (CFR3)
CFR3<31:30>
: DRV0 (XTAL_OUT) control bits.
These bits set the drive strength of the buffered reference
00 = OFF
(default)
01 = Low drive strength
10 = Mid drive strength
11 = High drive strength
CFR3<29:27>
:
Open
. Leave these bits clear.
CFR3<26:24>
:
VCO Selection Bits.
As per the table below, these bits set the VCO for the appro-
priate range.
Bits
Min
000
420MHz
001
485MHz
010
560MHz
011
655MHz
100
830MHz
101
920MHz
11x
PLL WILL NOT FUNCTION
Max
485MHz
560MHz
655MHz
830MHz
920MHz
1000MHz
CFR3<21:19>
:
Charge Pump Current Bits
As per the table below, these bits set the charge pump
output current.
CFR3<21:19>
Charge Pump Current (
μ
A)
000
200
001
225
010
250
011
275
100
300
101
325
110
350
111
375
Table 6 Charge Pump Output Current Settings
CFR3<18:16>
:
OPEN
. Leave these bits clear
CFR3<15>
:
REFCLK Input Divider Disable bit.
When
CFR3<15>
= 0 The AD9957 REFCLK input divider
is bypassed. The internal sysclk fed to the device (or the
clock multiplier) equals the REFCLK rate
When
CFR3<15>
= 1 (default) The AD9957 REFCLK input
divider is enabled (to ÷2). The internal sysclk fed to the de-
vice (or the clock multiplier) is equal to the REFCLK rate.
CFR3<14>
:
OPEN
This bit is used strictly for testing, leave SET.
CFR3<13:9>
:
OPEN
These bits are used for testing; leave CLEAR.
CFR3<8>
:
PLL Enable bit.
When
CFR3<8>
= 0
(default).
The AD9957 reference clock
rate equals the DAC clock sampling rate. The PLL is by-
passed and the clock multiplier is powered down.
When
CFR3<8>
= 1, The AD9957 reference clock rate
times the PLL Multiplier bit (integer equivalent) equals the
DAC clock sampling rate.
CFR3<7:1
>:
REFCLK Multiplier bits.
These bits make up the 8-bit word that is the multiplication
factor used by the PLL Clock Multiplier circuitry. The
decimal equivalent of the binary value of these bits is the
multiplication factor. Only certain values are valid (See Ta-
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