參數(shù)資料
型號: AD9956YCPZ1
廠商: Analog Devices, Inc.
英文描述: 2.7 GHz DDS-Based AgileRF
中文描述: 2.7千兆赫基于DDS的AgileRF
文件頁數(shù): 19/32頁
文件大?。?/td> 805K
代理商: AD9956YCPZ1
AD9956
CML DRIVER
For clocking applications, an on-chip current mode logic
(CML) driver is included. This CML driver generates very low
jitter clock edges. The outputs of the CML driver are current
outputs and drives PECL levels when terminated into a 100
load. The base output current of the driver is programmed by
attaching a resistor from the DRV_RSET pin to ground (nomi-
nally 4.02 k for a continuous current of 7.2 mA). An optional
on-chip current programming resistor is enabled by setting a bit
in the control register. The rising edge and falling edge slew
rates are independently programmable to help control over-
shoot and ringing through the application of surge current
during rising edge transitions and falling edge transitions (see
Figure 27). There is a default surge current of 7.6 mA on the
rising edge and 4.05 mA on the falling edge. Bits in the control
register enable additional rising edge and falling edge surge
current, as well disable the default surge current (see the
Control Function Register Descriptions section for details). The
CML driver can be driven by the
Rev. 0 | Page 19 of 32
RF divider input
RF divider output
PLLOSC input
I(t)
t
~250ps
~250ps
RISING EDGE SURGE
CONTINUOUS
FALLING EDGE SURGE
CONTINUOUS
0
Figure 27. Rising Edge and Falling Edge Surge Current Output of the
CML Clock Driver, as Opposed to the Steady State Continuous Current
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9956YCPZ-REEL1 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF
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