參數(shù)資料
型號(hào)： AD9927
廠商： Analog Devices, Inc.
英文描述： 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
中文描述： 14位CCD信號(hào)處理器與V - Driver和精密TimingTM發(fā)生器
文件頁(yè)數(shù)： 77/100頁(yè)
文件大?。?/td> 784K
代理商： AD9927
AD9927
Table 46. Standby Mode Operation (Standby Polarities for XV, XSUBCK, GPO Outputs are Programmable)
I/O Block
Standby3 (Default)
1, 2
OUTCONTROL = Low
2
AFE
Off
No change
Timing Core
Off
No change
CLO Oscillator
Off
No change
CLO
Low
No change
H1
High-Z
Low
H2
High-Z
High
H3
High-Z
Low
H4
High-Z
High
H5
High-Z
Low
H6
High-Z
High
H7
High-Z
Low
H8
High-Z
High
HL
High-Z
Low
RG
High-Z
Low
VD
Low
VDHDPOL value
HD
Low
VDHDPOL value
DCLK
Low
Running
DOUT
Low
Low
XV1 to XV24
Low
Low
XSUBCK
Low
Low
GPO1 to GPO8
Low
Low
1
To exit Standby3, write 00 to STANDBY (Address 0x00, Bits [1:0]), and then reset the timing core after 500 μs to guarantee proper settling of the oscillator and external crystal.
2
Standby3 mode takes priority over OUTCONTROL for determining the output polarities.
3
These polarities assume OUTCONTROL = high because OUTCONTROL = low takes priority over Standby1 and Standby2.
4
Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).
Rev. 0 | Page 77 of 100
Standby2
3, 4
Off
Off
Off
Low
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
VDHDPOL value
VDHDPOL value
Low
Low
Low
Low
Low
Standby1
3, 4
Only REFT, REFB on
On
On
Running
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Running
Running
Running
Low
Low
Low
Low
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