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參數(shù)資料
| 型號： | AD9923ABBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 3/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923ABBCZRL |
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AD9923A
SPECIFICATIONS
Rev. 0 | Page 3 of 88
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
AFETG POWER SUPPLY VOLTAGES
AVDD
TCVDD
RGVDD
HVDD
DRVDD
DVDD
V-DRIVER POWER SUPPLY
VOLTAGES
VDD1, VDD2
VH1, VH2
VL1, VL2
VM1, VM2
VLL
VMM
AFETG POWER DISSIPATION
Total
Standby 1 Mode
Standby 2 Mode
Standby 3 Mode
Power from HVDD Only
1
Power from RGVDD Only
Power from AVDD Only
Power from TCVDD Only
Power from DVDD Only
Power from DRVDD Only
V-DRIVER POWER DISSIPATION
2
Conditions/Comments
AFE analog supply
Timing Core Analog Supply
RG Driver
HL, H1 to H4 Drivers
Data Output Drivers
Digital
Min
25
65
2.7
2.7
2.7
2.7
2.7
2.7
Typ
3.0
3.0
3.0
3.0
3.0
3.0
Max
+85
+150
3.6
3.6
3.6
3.6
3.6
3.6
Unit
°C
°C
V
V
V
V
V
V
V-Driver Logic
V-Driver High Supply
V-Driver Low Supply
V-Driver Mid Supply
SUBCK Low Supply
SUBCK Mid Supply
36 MHz, 3.0 V supply, 400 pF total H-load, 20 pF RG load
VH1, VH2 = +15 V; VL1, VL2 = 7.5 V; VM1, VM2 = 0 V; VDD1, VDD2 =
3.3 V; all V-driver inputs tied low
+2.7
+11.5
8.5
1.5
8.5
4.0
+3.0
+15.0
7.5
0.0
7.5
0.0
335
105
1
1
130
10
75
40
75
5
+3.6
+16.5
5.5
+1.5
5.5
+1.5
V
V
V
V
V
V
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
VH1, VH2
VL1, VL2
VM1, VM2
VDD1, VDD2
MAXIMUM CLOCK RATE (CLI)
1
The total power dissipated by the HVDD supply can be approximated using the equation
Total HVDD Power
= [
C
LOAD
×
HVDD
×
Pixel Frequency
] ×
HVDD
Reducing the H-load and/or using a lower HVDD supply reduces the power dissipation. C
LOAD
is the total capacitance seen by all H-outputs.
2
V-driver power dissipation depends on the frequency of operation and the load they are driving. All inputs to the V-driver were tied low for the
measurements in Table 1.
36
5
2.5
0
0.5
mW
mW
mW
mW
MHz
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