1START POLARITY (CLAMP AND BLANK RE" />
參數(shù)資料
型號： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 30/112頁
文件大小： 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 24 of 112
3
2
1
HD
CLPOB
PBLK
PROGRAMMABLE SETTINGS:
1START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION.
ACTIVE
06
87
8-
02
7
Figure 27. Clamp and Preblank Pulse Placement
NO CLPOB SIGNAL
FOR LINE 600
VD
HD
NO CLPOB SIGNAL
FOR LINES 6 TO 8
CLPMASKSTART1 = 6
CLPMASKEND1 = 9
0
1
2
597
598
CLPMASKSTART2 = 600
CLPMASKEND2 = 601
CLPOB
06
87
8-
0
28
Figure 28. CLPOB Masking Example
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 29 is similar to
the timing of CLPOB and PBLK; however, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, separate
masking polarity controls for each H-clock phase designate the
polarity of the horizontal clock signals during the blanking period.
Setting HBLKMASK_H1 high sets H1—and, therefore, H3, H5,
and H7—low during the blanking, as shown in Figure 30. As with
the CLPOB and PBLK signals, HBLK registers are available in
each V-sequence, allowing different blanking signals to be used
with different vertical timing sequences.
The AD9920A supports two modes of HBLK operation. HBLK
Mode 0 supports basic operation and pixel mixing HBLK oper-
ation. HBLK Mode 1 supports advanced HBLK operation.
The following sections describe each mode in detail. Register
parameters are described in detail in Table 12.
HBLK Mode 0 Operation
There are six toggle positions available for HBLK. Normally, only
two of the toggle positions are used to generate the standard
HBLK interval. However, the additional toggle positions can be
used to generate special HBLK patterns, as shown in Figure 31.
The pattern in this example uses all six toggle positions to gen-
erate two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.
Separate toggle positions are available for even and odd lines. If
alternation is not needed, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Multiple repeats of the HBLK signal are enabled by setting the
HBLKLEN and HBLKREP registers along with the six toggle
positions (four are shown in Figure 32).
Generating HBLK Line Alternation
HBLK Mode 0 provides the ability to alternate different HBLK
toggle positions on even and odd lines. HBLK line alternation
can be used alone or in conjunction with V-pattern odd/even
and HBLK section). Separate toggle positions are available for
even and odd lines. If even/odd line alternation is not needed,
the same values should be loaded into the registers for even
(HBLKTOGE) and odd (HBLKTOGO) lines.
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