參數(shù)資料
型號(hào)： AD9889BBSTZ-80
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 10/12頁(yè)
文件大小： 0K
描述： IC TRANSMITTER HDMI/DVI 80LQFP
標(biāo)準(zhǔn)包裝： 90
類(lèi)型： HDMI，DVI 發(fā)射器
應(yīng)用： 錄音機(jī)，機(jī)頂盒
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤(pán)
配用： AD9889B/PCBZ-ND - KIT EVALUATION FOR AD9889B
AD9889B
Rev. A | Page 7 of 12
J
K
A
B
C
D
E
F
G
H
10
8
7
6
3
2
1
95
4
62
91
-00
4
BOTTOM VIEW
(Not to Scale)
0
Figure 4. 76-Ball BGA Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Type1
BGA
LFCSP
LQFP
D10, D9, C10,
C9, A10, B10,
A9, B9, A8, B8,
A7, B7, A6, B6,
A5, B5, A4, B4,
A3, B3, A2, B2,
A1, B1
39 to 47,
50 to 63, 2
50 to 58, 65 to
78, 2
D[23:0]
I
Video Data Input. Digital input in RGB or YCbCr format.
Supports CMOS logic levels from 1.8 V to 3.3 V.
D1
6
CLK
I
Video Clock Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
C2
3
DE
I
Data Enable Bit for Digital Video. Supports CMOS logic levels
from 1.8 V to 3.3 V.
C1
4
HSYNC
I
Horizontal Sync Input. Supports CMOS logic levels from
1.8 V to 3.3 V.
D2
5
VSYNC
I
Vertical Sync Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
J3
18
23
EXT_SWG
I
Sets Internal Reference Currents. Place 887 Ω resistor
(1% tolerance) between this pin and ground.
K3
20
25
HPD
I
Hot Plug Detect Signal. This indicates to the interface
whether the receiver is connected. Supports 1.8 V to 5.0 V
CMOS logic levels.
E2
7
S/PDIF
I
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is
the audio input from a Sony/Philips digital interface.
Supports CMOS logic levels from 1.8 V to 3.3 V.
E1
8
MCLK
I
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4.
Set to 128 × sampling frequency (fS), 256 × fS, 384 × fS, or
512 × fS. Supports 1.8 V to 3.3 V CMOS logic levels.
F2, F1, G2, G1
9 to 12
I2S[3:0]
I
I2S Audio Data Inputs. These represent the eight channels of
audio (two per input) available through I2S. Supports CMOS
logic levels from 1.8 V to 3.3 V.
H2
13
SCLK
I
I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
H1
14
LRCLK
I
Left/Right Channel Selection. Supports CMOS logic levels
from 1.8 V to 3.3 V.
J72
332
PD/A0
I
Power-Down Control and I2C Address Selection. The I2C
address and the PD polarity are set by the PD/A0 pin state
when the supplies are applied to the AD9889B. Supports
1.8 V to 3.3 V CMOS logic levels.
K1, K2
21, 22
27, 28
TxC/TxC+
O
Differential Clock Output. Differential clock output at pixel
clock rate; supports TMDS logic level.
K10, J10
30, 31
37, 38
Tx2/Tx2+
O
Differential Output Channel 2. Differential output of the red
data at 10× the pixel clock rate; supports TMDS logic level.
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