參數(shù)資料
型號: AD9877ABSZ
廠商: Analog Devices Inc
文件頁數(shù): 9/36頁
文件大?。?/td> 0K
描述: IC PROCESSOR FRONT END 100MQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
通道數(shù): 3
功率(瓦特): 1.17W
電壓 - 電源,模擬: 3.3V
電壓 - 電源,數(shù)字: 3.3V
封裝/外殼: 100-BQFP
供應(yīng)商設(shè)備封裝: 100-MQFP(14x20)
包裝: 托盤
AD9877
Rev. B | Page 17 of 36
Σ-Δ OUTPUTS
The AD9877 contains two independent Σ-Δ outputs that
provide a digital logic bit stream with an average duty cycle that
varies between 0% and (4095/4096)%, depending on the
programmed code, as shown in Figure 19.
These bit streams can be low-pass filtered to generate
programmable dc voltages of
VDC = (Σ-Δ Code/4096)(VH) + VL
where:
VH = VDRVDD 0.6 V.
VL = 0.4 V.
In set-top box and cable modem applications, the outputs can
be used to control external variable gain amplifiers and RF
tuners. A simple single-pole RC low-pass filter provides
sufficient filtering (Figure 20).
In more demanding applications where additional gain, level
shift, or drive capability is required, a first or second order
active filter might be considered for each Σ-Δ output (Figure 21).
0x000
0x001
0x002
0x800
0xFFF
4096
× 8 t
MCLK
4096
× 8 t
MCLK
8
tMCLK
8
tMCLK
02716-019
Figure 19. Σ-Δ Output Signals
Σ-Δ
CONTROL
WORD 0
CONTROL
WORD 1
12
SIGMA-DELTA 0
SIGMA-DELTA 1
R
C
DC (0.4 TO
DRVDD – 0.6V)
DC (0.4 TO
DRVDD – 0.6V)
TYPICAL:
R = 50k
Ω
C = 0.01
μF
f–3dB = 1/(2πRC) = 318Hz
÷8
MCLK
AD9877
02716-
020
Figure 20. Σ-Δ RC Filter
R
C
VOUT = (VSD + VOFFSET) (1 + R/R1)/2
TYPICAL:
R = 50k
Ω
C = 0.01
μF
f–3dB = 1/(2πRC) = 318Hz
AD9877
R
VOFFSET
OP250
R1
R
C
VSD
VOUT
Σ-Δ
02716-021
Figure 21. Σ-Δ Active Filter with Gain and Offset
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