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參數(shù)資料
| 型號： | AD9853AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Digital OPSK/16-QAM Modulator |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP44 |
| 封裝： | METRIC, QFP-44 |
| 文件頁數(shù)： | 15/31頁 |
| 文件大?。?/td> | 335K |
| 代理商： | AD9853AS |
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AD9853
–15–
REV. C
THEORY OF OPERATION
The AD9853 is a highly integrated modulator function that has
been specifically designed to meet the requirements of the HFC
upstream function for both interoperable and proprietary system
implementations. The AD8320 is a companion cable driver
amplifier with a digitally-programmable gain function, that
interfaces to the AD9853 modulator and directly drives the
cable plant with the modulated carrier. Together, the AD9853
and AD8320 provide an easily implementable transmitter solu-
tion for the HFC return-path requirement.
CONTROL AND DATA INTERFACE
As shown in the device’s block diagram on the front page, the
various transmit parameters, which include the input data rate,
modulation format, FEC and randomizer configurations, as well
as all the other modulator functions, are programmed into the
AD9853 via a serial control bus. The AD8320 cable driver amp
gain can be programmed directly from the AD9853 via a 3-wire
bus by writing to the appropriate AD9853 register. The AD9853
also contains dedicated pins for FEC enable/disable and a RESET
function.
Note: T
X
ENABLE pin must be held low for the duration of all
serial control bus operations.
The AD9853’s serial control bus consists of a bidirectional data
line and a clock line. Communication is initiated upon a start
condition, which is defined as a high-to-low transition of the
data line while the clock is held high. Communication terminates
upon a stop condition, which is defined as a low-to-high transi-
tion in the data line while the clock is held high. Ordinarily, the
data line transitions only while the clock line is low to avoid a
start or stop condition. Data is always written or read back in
8-bit bytes followed by a single acknowledge bit. The micro-
controller or ASIC (i.e., the bus master) transfers eight data bits
and the AD9853 (i.e., the slave) issues the acknowledge bit. The
acknowledge bit is active low and is clocked out on every ninth
clock pulse. The bus master must three-state the data line dur-
ing the ninth clock pulse and allow the AD9853 to pull it low.
A valid write sequence consists of a minimum of three bytes.
This means 27 clock pulses (three bytes with nine clock pulses
each) must be provided by the bus master. The first byte is a
chip address byte that is predefined except for Bit Positions 1
and 0. Bit Positions 7, 6, 5, 4 and 3 must be zero. Bit Position 2
must be a one. Bit 1 is set according to the external address pin
on the AD9853 (1 if the pin is connected to +V
S
; 0 if the pin
is grounded). Bit 0 is set to 1 if a read operation is desired, 0 if a
write operation is desired. The second byte is a register address
with valid addresses between 00h and 49h. An address which is
outside of this range will not be acknowledged. The third byte is
data for the address register. Multiple data bytes are allowed
and loaded sequentially. That is, the first data byte is written to
the addressed register and any subsequent data bytes are written
to subsequent register addresses. It is permissible to write all
registers by issuing a valid chip address byte, then an address
byte of 00h and then 72 (48h) data bytes. Address 49h must be
written independently, that is, not in conjunction with any other
address.
A valid read sequence consists of a minimum of four bytes (refer
to Figure 27). This means the bus master must provide 36 clock
pulses (four bytes with nine clock pulses each). Like the write
sequence, the first two bytes are the Chip Address Byte, with the
read/write bit set to 0, and the readback register address. After
the slave provides an acknowledge at the end of the register
address, the master must present a START condition on the
bus, followed by the Chip Address Byte with the read/write bit
set to a 1. The slave proceeds to provide an acknowledge. Dur-
ing the next eight clocks the slave will write to the bus from the
register address. The master must provide an acknowledge on
the ninth clock of this byte. Any subsequent clocks from the
master will force the slave to read back from subsequent regis-
ters. At the end of the read-back cycle, the MASTER must force
a “no-acknowledge” and then a STOP condition. This will take
the SLAVE out of read-back mode. Not all of the serial control
bus registers can be read back. Registers (06h–11h) and (1Eh–
47h) are write only. Also, like the writing procedure, register
49h must be read from independently.
INPUT DATA SYNCHRONIZATION
The serial input data interface consists of two pins, the serial
data input pin and a T
X
ENABLE pin. The input data arrives at
the bit rate and is framed by the T
X
ENABLE signal as shown in
Figure 26. A high frequency sampling clock continuously
samples the T
X
ENABLE signal to detect the rising edge. Once
the rising edge of T
X
ENABLE is detected, an internal sampler
strobes the serial data at the correct point in time relative to the
positive T
X
ENABLE transition and then continues to sample at
the correct interval based on the programmed Input Data rate.
For proper synchronization of the AD9853, 1) the input burst
data must be accurately framed by T
X
ENABLE and 2) the
input data rate must be an exact even submultiple of the system
clock. Typically this will require that the input data rate clock be
synchronized with reference clock.
REED-SOLOMON ENCODER
The AD9853 contains a programmable Reed-Solomon (R-S)
encoder capable of generating an (N, K) code where
N
is the
code word length and
K
is the message length.
Error correction becomes vital to reliable communications when
the transmission channel conditions are less than ideal. The
original message can be precisely reconstructed from a cor-
rupted transmission as long as the number of message errors is
within the encoder’s limits. When forward error correction
(FEC) is engaged, either through the serial control interface
bus or hardware (logic high at Pin 5), it is implemented using
the following MCNS-compatible field generator and primitive
polynomials:
Primitive Polynomial:
p
(
x
) =
x
8
+
x
4
+
x
3
+
x
2
+
1
Code Generator Polynomial:
g
(
x
) = (
x
+
a
0
)(
x
+
a
1
)(
x
+
a
2
)
. . . (
x
+
a
2t – 1
)
The code-word structure is defined as follows:
N
=
K
+ 2
t
(
bytes
)
where:
N
= code-word length
K
= message length (in bytes), programmable from 16–255
t
=
number of byte errors that can be corrected programmable
from 0–10.
A
Code Word
is the sum of the
Message Length
(in bytes) and
number of
Check Bytes
required to correct byte errors at the
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