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參數(shù)資料
| 型號： | AD9850BRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | CMOS, 125 MHz Complete DDS Synthesizer |
| 中文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PDSO28 |
| 封裝： | MO-150AH, SSOP-28 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 378K |
| 代理商： | AD9850BRS |
AD9850
–5–
REV. E
Table I. Lead Function Descriptions
Pin
No.
Mnemonic
Function
4–1,
28–25
5, 24
6, 23
7
8
D0–D7
8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and 8-bit phase/
control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data word.
Digital Ground. These are the ground return leads for the digital circuitry.
Supply Voltage Leads for digital circuitry.
Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.
Frequency Update. On the rising edge of this clock, the DDS will update to the frequency (or phase)
loaded in the data input register, it then resets the pointer to Word 0.
Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at
1/2 V supply. The rising edge of this clock initiates operation.
Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).
Supply Voltage for the analog circuitry (DAC and comparator).
This is the DAC’s external R
SET
connection. This resistor value sets the DAC full-scale output current. For
normal applications (
F
S
I
OUT
= 10
mA
), the value for R
SET
is 3.9 k
connected to ground. The R
SET
/I
OUT
relationship is:
I
OUT
= 32 (1.248 V/R
SET
).
Output Complement. This is the comparator’s complement output.
Output True. This is the comparator’s true output.
Inverting Voltage Input. This is the comparator’s negative input.
Noninverting Voltage Input. This is the comparator’s positive input.
DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should
normally be considered a “no connect” for optimum performance.
The Complementary Analog Output of the DAC.
Analog Current Output of the DAC.
Reset. This is the master reset function; when set high it clears all registers (except the input register) and
the DAC output will go to Cosine 0 after additional clock cycles—see Figure 19.
DGND
DVDD
W_CLK
FQ_UD
9
CLKIN
10, 19
11, 18
12
AGND
AVDD
R
SET
13
14
15
16
17
QOUTB
QOUT
VINN
VINP
DACBL (NC)
20
21
22
IOUTB
IOUT
RESET
PIN CONFIGURATIONS
17
16
15
20
19
18
28
27
26
25
24
23
22
21
14
13
12
11
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD9850
D3
D7 MSB/SERIAL LOAD
D6
D5
D4
D2
D1
LSB D0
RESET
DVDD
DGND
DGND
DVDD
W CLK
FQ UD
CLKIN
AGND
AGND
IOUTB
IOUT
AVDD
R
SET
QOUTB
QOUT
AVDD
VINN
VINP
DACBL (NC)
NC = NO CONNECT
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| AD9850BRS-REEL | 功能描述:IC DDS SYNTHESIZER CMOS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9850BRSZ | 功能描述:IC DDS SYNTHESIZER CMOS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9850BRSZ | 制造商:Analog Devices 功能描述:IC, DDS, 125MHz, SSOP-28 |
| AD9850BRSZ-REEL | 功能描述:IC DDS SYNTHESIZER CMOS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9851 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 180 MHz DDS/DAC Synthesizer |
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