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參數(shù)資料
| 型號： | AD9804JST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Complete 10-Bit 18 MSPS CCD Signal Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 379K |
| 代理商： | AD9804JST |
REV. 0
AD9804
–6–
PROGRAMMING THE SERIAL INTERFACE
Table I. VGA Gain Register Contents (Default Value x096)
MSB
D9
LSB
D0
D8
D7
D6
D5
D4
D3
D2
D1
Gain (dB)
0
0
0
1
0
1
1
1
1
1
1
1
6.0
39.965
40.0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
SDATA
SCK
SL
RNW
ADDRESS BITS
0
0
0
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
t
DS
t
DH
t
LS
t
LH
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ, NOT WRITE. SET LOW FOR WRITE OPERATION.
3. INTERNAL VGA GAIN REGISTER UPDATE OCCURS AT SL RISING EDGE.
DATA BITS
Figure 3. Serial Write Operation
SDATA
SCK
SL
RNW
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
t
DS
t
DH
t
LS
t
LH
NOTES:
1. RNW = READ, NOT WRITE. SET HIGH FOR READ OPERATION.
2. THE RNW BIT AND THE FOUR ADDRESS BITS MUST BE WRITTEN TO THE AD9804. SDATA IS LATCHED ON SCK RISING EDGES.
3. SERIAL DATA FROM VGA GAIN REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK FALLING EDGES.
t
DV
ADDRESS BITS
0
0
1
0
DATA BITS
Figure 4. Serial Readback Operation
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