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參數(shù)資料
型號(hào)： AD9779A-DPG2-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/56頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR AD9779A
設(shè)計(jì)資源： Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016)
Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017)
Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018)
Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019)
Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020)
Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
AD9788-79A Eval Brd Schematic
AD9779A-DPG2-EBZ BOM
AD9779A-DPG2-EBZ Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： *
DAC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 1G
數(shù)據(jù)接口： 串行
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9779A
AD9776A/AD9778A/AD9779A
Rev. B | Page 35 of 56
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Figure 64. Interpolation/Modulation Combination of fDAC/8 Filter
Figure 67. Interpolation/Modulation Combination of 3fDAC/8 Filter
Shifted mode filter responses allow the pass band to be centered
around ±0.5 fDATA, ±1.5 fDATA, ±2.5 fDATA, and ±3.5 fDATA. Switching to
the shifted mode response does not affect the center frequency
of the signal. Instead, the pass band of the filter is simply shifted.
For example, use the response shown in Figure 67 and assume
the signal in-band is a complex signal over the bandwidth 3.2 fDATA
to 3.3 fDATA. If the shifted mode filter response is then selected,
the pass band becomes centered at 3.5 fDATA. However, the signal
remains at the same place in the spectrum. The shifted mode
capability allows the filter pass band to be placed anywhere in
the DAC Nyquist bandwidth.
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fOUT (× Input Data Rate)
AT
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The AD9776A/AD9778A/AD9779A are dual DACs with
internal complex modulators built into the interpolating filter
response. In dual channel mode, the devices expect the real and
imaginary components of a complex signal at Digital Input Port 1
and Digital Input Port 2 (I and Q, respectively). The DAC outputs
then represent the real and imaginary components of the input
signal, modulated by the complex carrier (fDAC/2, fDAC/4, or fDAC/8).
Figure 65. Interpolation/Modulation Combination of fDAC/8 Filter
10
–100
–4
4
–3
–2
–1
0123
0
–10
–20
–30
–40
–50
–60
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fOUT (× Input Data Rate)
AT
T
E
N
UAT
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63
With Register 0x02, Bit 6, set, the device accepts interleaved data
on Port 1 in the I, Q, I, Q … sequence. Note that in interleaved
mode, the channel data rate at the beginning of the I and Q data
paths is now half the input data rate because of the interleaving.
The maximum input data rate is still subject to the maximum
specification of the device. This limits the synthesis bandwidth
available at the input in interleaved mode.
With Register 0x02, Bit 5 (the real mode bit), set, the Q channel
and the internal I and Q digital modulation are turned off. The
output spectrum at the I DAC then represents the signal at
Digital Input Port 1, interpolated by 1×, 2×, 4×, or 8×.
The general recommendation is that if the desired signal is
within ±0.4 × fDATA, use the nonshifted filter mode. Outside of
this, the shifted filter mode should be used. In any situation, the
total bandwidth of the signal is less than 0.8 × fDATA.
Figure 66. Interpolation/Modulation Combination of 2fDAC/8 Filter
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