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參數(shù)資料
| 型號： | AD9774ASZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32MSPS 44MQFP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 800 |
| 系列： | TxDAC+® |
| 設置時間： | 35ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 1.13W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 32M |
AD9774
–6–
REV. B
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1, 19, 40, 44
DCOM
Digital Common.
2
DB13
Most Significant Data Bit (MSB).
3–14
DB12–DB1
Data Bits 1–12.
15
DB0
Least Significant Data Bit (LSB).
16, 17, 42
NC
No Internal Connection.
18, 41
DVDD
Digital Supply Voltage (+2.7 V to +5.5 V).
20
CLK IN/OUT
Clock Input when PLL Clock Multiplier enabled. Clock Output when PLL Clock Multiplier
disabled. Data latched on rising edge.
21
PLLLOCK
Phase Lock Loop Lock Signal. Active High indicates PLL is locked to input clock.
22
CLK4
×IN
External 4
× Clock Input when PLL is disabled. No Connect when internal PLL is active.
23
PLLDIVIDE
PLL Range Control Pin. Connect to PLLCOM if CLKIN is above 10 MSPS. Connect to
PLLVDD if CLKIN is between 10 MSPS and 5.5 MSPS.
24
VCO IN/EXT
Internal Voltage Controlled Oscillator (VCO) Enable/Disable Pin. Connect to PLLVDD to enable
VCO. Connect to PLLCOM to disable VCO and drive CLK4
×IN with external VCO output.
25
LPF
PLL Loop Filter Node. Connect to external VCO control input if internal VCO disabled.
26
PLLVDD
Phase Lock Loop (PLL) Supply Voltage (+2.7 V to +5.5 V). Must be set to similar voltage as DVDD.
27
PLLCOM
Phase Lock Loop Common.
28
PLLENABLE
Phase Lock Loop Enable. Connect to PLLVDD to enable. Connect to PLLCOM to disable.
29
UNUSED
Factory Test. Leave Open.
30
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
31
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO
to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to
ACOM). Requires 0.1
F capacitor to ACOM when internal reference activated.
32
FSADJ
Full-Scale Current Output Adjust.
33
REFCOMP
Noise Reduction Node. Add 0.1
F to AVDD.
34
ACOM
Analog Common.
35
AVDD
Analog Supply Voltage (+2.7 V to +5.5 V).
36
IOUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
37
IOUTA
DAC Current Output. Full-scale current when all data bits are 1s.
38
ICOMP
Internal bias node for switch driver circuitry. Decouple to ACOM with 0.1
F capacitor.
39
SLEEP
Power-Down Control Input. Active High. Connect to DCOM if not used.
43
SNOOZE
SNOOZE Control Input. Deactivates 4
× interpolation filter to reduce digital power consumption
only. Active High. Connect to DCOM if not used.
PIN CONFIGURATION
3
4
5
6
7
1
2
10
11
8
9
40 39 38
41
42
43
44
36 35 34
37
29
30
31
32
33
27
28
25
26
23
24
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
12 13 14 15 16 17 18 19 20 21 22
REFCOMP
FSADJ
REFIO
REFLO
UNUSED
PLLENABLE
PLLCOM
AD9774
DCOM
DB13
DB12
DB11
DB10
DB9
DB8
NC = NO CONNECT
DB7
DB6
DB5
DB4
PLLVDD
LPF
VCO IN/EXT
PLLDIVIDE
DB3
DB2
DB1
DB0
NC
DVDD
DCOM
CLK
IN/OUT
PLLLOCK
CLK4
IN
IOUTB
ACOM
DCOM
SNOOZE
DVDD
IOUTA
AVDD
DCOM
SLEEP
ICOMP
NC
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