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| 型號： | AD9772AASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/40頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 160MSPS 48-LQFP |
| 產(chǎn)品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| 系列： | TxDAC+® |
| 設置時間： | 11ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 272mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 160M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
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AD9772A
Rev. C | Page 27 of 40
of 20 mA flows through the equivalent RLOAD of 25 Ω. In this
case, RLOAD represents the equivalent load resistance seen by
IOUTA. The unused output (IOUTB) should be connected directly to
ACOM. Different values of IOUTFS and RLOAD can be selected as long
as the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL), as
discussed in the Analog Outputs section of this data sheet. For
optimum INL performance, the single-ended, buffered voltage
output configuration is suggested.
AD9772A
IOUTA
IOUTB
50
VOUTA = 0V TO 0.5V
IOUTFS = 20mA
0
225
3-
05
0
Figure 50. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
Figure 51 shows a single-ended, buffered output configuration
in which the op amp U1 performs an I-V conversion on the
AD9772A output current. U1 maintains IOUTA (or IOUTB) at virtual
ground, thus minimizing the nonlinear output impedance effect
on the INL performance of the DAC, as discussed in the Analog
Outputs section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates is often
limited by U1’s slewing capabilities. U1 provides a negative
unipolar output voltage, and its full-scale output voltage is
simply the product of RFB and IOUTFS. The full-scale output
should be set within U1’s voltage output swing capabilities
by scaling IOUTFS and/or RFB. An improvement in ac distortion
performance may result in a reduced IOUTFS because the signal
current that U1 will be required to sink is subsequently reduced.
AD9772A
IOUTA
IOUTB
U1
RFB
200
COPT
IOUTFS = 10mA
VOUT = –IOUTFS × RFB
0
225
3-
05
1
Figure 51. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
The AD9772A contains the following power supply inputs:
AVDD, DVDD, CLKVDD, and PLLVDD. The AD9772A is
specified to operate over a 3.1 V to 3.5 V supply range, thus
accommodating a 3.3 V power supply with up to ±6%
regulation. However, the following two conditions must be
adhered to when selecting power supply sources for AVDD,
DVDD, CLKVDD, and PLLVDD:
PLLVDD = CLKVDD = 3.1 V to 3.5 V when the PLL clock
multiplier is enabled (otherwise, PLLVDD = PLLCOM)
DVDD = CLKVDD ± 0.30 V
To meet the first condition, PLLVDD must be driven by the
same power source as CLKVDD, with each supply input
independently decoupled using a 0.1 μF capacitor connected to
its respective ground. To meet the second condition, CLKVDD
can share the same power supply source as DVDD by using the
decoupling network shown in Figure 52 to isolate digital noise
from the sensitive CLKVDD (and PLLVDD) supply. Alternatively,
separate precision voltage regulators can be used to ensure that
the second condition is met.
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing, and supply bypassing and grounding.
circuit board ground, power, and signal plane layouts that are
implemented on the AD9772A evaluation board.
Proper grounding and decoupling should be a primary
objective in any high speed, high resolution system. The
AD9772A features separate analog and digital supply and
ground pins to optimize the management of analog and digital
ground currents in a system. AVDD, CLKVDD, and PLLVDD
must be powered from a clean analog supply and decoupled to
their respective analog common (that is, ACOM, CLKCOM, and
PLLCOM) as close to the chip as physically possible. Similarly, the
digital supplies (DVDD) should be decoupled to DCOM.
For applications requiring a single 3.3 V supply for the analog,
digital, and phase-lock loop supplies, a clean AVDD and/or
CLKVDD can be generated using the circuit shown in Figure 52.
The circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low ESR-
type electrolytic and tantalum capacitors.
+
–
100F
ELECTROLYTIC
+
–
10F TO 22F
TANTALUM
0.1F
CERAMIC
AVDD
ACOM
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER
SUPPLY
FERRITE
BEADS
02253-
052
Figure 52. Differential LC Filter for 3.3 V
Maintaining low noise on power supplies and ground is critical
for achieving optimum results from the AD9772A. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards, such as bypassing and shielding
current transport. In mixed-signal designs, the analog and
digital portions of the board should be distinct from each other,
with the analog ground plane confined to the areas covering the
analog signal traces, and the digital ground plane confined to
areas covering the digital interconnects.
All analog ground pins of the DAC, reference, and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path to
inch wide underneath or within inch of the DAC to maintain
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772AASTZRL | 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9772A-EB | 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk |
| AD9772A-EBZ | 功能描述:BOARD EVAL FOR AD9772A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9772AST | 制造商:Rochester Electronics LLC 功能描述:14 BIT DAC W/2X INTERPOLA - Tape and Reel |
| AD9772EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
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