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參數(shù)資料
| 型號： | AD9772 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit,150 MSPS T×DAC+TM with 2× Interpolation Filter(單電源,過采樣,14位D/A轉(zhuǎn)換器) |
| 中文描述： | 14位，150 MSPS的DAC的商標(biāo)厚× 2 ×插值濾波器（單電源，過采樣，14位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 20/30頁 |
| 文件大?。?/td> | 341K |
| 代理商： | AD9772 |
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REV. 0
AD9772
–20–
some additional signal gain. The op amp must operate from a
dual supply since its output is approximately
±
1.0 V. A high
speed amplifier, capable of preserving the differential perform-
ance of the AD9772 while meeting other system level objectives
(i.e., cost, power), should be selected. The op amp’s differential
gain, its gain setting resistor values and full-scale output swing
capabilities should all be considered when optimizing this circuit.
The differential circuit shown in Figure 43 provides the neces-
sary level shifting required in a single supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9772 and the op amp, is also used to level-shift the differ-
ential output of the AD9772 to midsupply (i.e., AVDD/2). The
AD8057 is a suitable op amp for this application.
AD9772
IOUTA
IOUTB
AD8057
C
OPT
25
V
25
V
225
V
225
V
500
V
1k
V
1k
V
AVDD
Figure 43. Single Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 44 shows the AD9772 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50
cable since the nominal full-scale current, I
OUTFS
, of
20 mA flows through the equivalent R
LOAD
of 25
. In this case,
R
LOAD
represents the equivalent load resistance seen by IOUTA.
The unused output (IOUTB) can be connected to ACOM
directly. Different values of I
OUTFS
and R
LOAD
can be selected as
long as the positive compliance range is adhered to. One addi-
tional consideration in this mode is the integral nonlinearity
(INL) as discussed in the Analog Output section of this data
sheet. For optimum INL performance, the single-ended, buff-
ered voltage output configuration is suggested.
AD9772
IOUTA
IOUTB
50
V
50
V
V
OUTA
= 0V TO +0.5V
I
OUTFS
= 20mA
Figure 44. 0 V to +0.5 V Unbuffered Voltage Output
SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 45 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9772
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, thus minimizing the nonlinear output impedance effect
on the DAC’s INL performance as discussed in the Analog
Output section. Although this single-ended configuration typi-
cally provides the best dc linearity performance, its ac distortion
performance at higher DAC update rates is often limited by
U1’s slewing capabilities. U1 provides a negative unipolar output
voltage and its full-scale output voltage is simply the product of
R
FB
and I
OUTFS
. The full-scale output should be set within U1’s
voltage output swing capabilities by scaling I
OUTFS
and/or R
FB
.
An improvement in ac distortion performance may result with a
reduced I
OUTFS
since the signal current U1 will be required to
sink will be subsequently reduced.
AD9772
IOUTA
IOUTB
U1
R
FB
200
V
200
V
C
OPT
I
OUTFS
= 10mA
V
OUT
= –I
OUTFS
3
R
FB
Figure 45. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
The AD9772 contains the four following power supply inputs:
AVDD, DVDD, CLKVDD and PLLVDD. The AD9772 is
specified to operate over a 2.7 V to 3.6 V supply range, thus
accommodating +3.0 V and/or 3.3 V power supplies with up to
±
10% regulation. However, the following two conditions
must
be adhered to when selecting power supply sources for AVDD,
DVDD, CLKVDD, and PLLVDD:
1. PLLVDD = CLKVDD when PLL Clock Multiplier enabled.
(Otherwise PLLVDD = PLLCOM)
2. DVDD = CLKVDD
±
0.30 V
To meet the first condition, PLLVDD must be driven by the
same power source as CLKVDD with each supply input inde-
pendently decoupled with a 0.1
μ
F capacitor to its respective
grounds. To meet the second condition, CLKVDD can share
the power supply source as DVDD, using the decoupling net-
work shown in Figure 46 to isolate digital noise from the sensi-
tive CLKVDD (and PLLVDD) supply. Alternatively, separate
precision voltage regulators can be used to ensure that condition
two is met.
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing and supply bypassing and grounding.
Figures 54–61
illustrate the recommended printed circuit board
ground, power and signal plane layouts that are implemented on
the AD9772 evaluation board.
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9772 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. AVDD, CLKVDD, and PLLVDD must be powered from
a clean analog supply and decoupled to their respective analog
common (i.e., ACOM, CLKCOM and PLLCOM) as close to
the chip as physically possible. Similarly, DVDD, the digital
supply, should be decoupled to DCOM.
For those applications requiring a single +3 V or +3.3 V supply
for both the analog, digital supply and Phase Lock Loop supply,
a clean AVDD and/or CLKVDD may be generated using the
circuit shown in Figure 46. The circuit consists of a differential
LC filter with separate power supply and return lines. Lower
noise can be attained using low ESR-type electrolytic and tanta-
lum capacitors.
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