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參數(shù)資料
| 型號(hào)： | AD9754ARZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 125MSPS 28-SOIC TR |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | TxDAC® |
| 設(shè)置時(shí)間： | 35ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 220mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 125M |
AD9754
–13–
REV. A
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9754 is positive edge triggered, and
so exhibits SNR sensitivity when the data transition is close to
this edge. In general, the goal when applying the AD9754 is to
make the data transitions close to the negative clock edge. This
becomes more important as the sample rate increases. Figure 23
shows the relationship of SNR to clock placement.
TIME (ns) OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE
68
–8
SNR
–
dB
64
60
56
52
48
44
40
–6
–4
–2
0
2
468
10
FS = 125MSPS
FS = 65MSPS
Figure 23. SNR vs. Clock Placement @ fOUT = 10 MHz
SLEEP MODE OPERATION
The AD9754 has a power-down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level “1” to the SLEEP pin. This digital input also con-
tains an active pull-down circuit that ensures the AD9754 re-
mains enabled if this input is left disconnected. The AD9754
takes less than 50 ns to power down and approximately 5
s to
power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9754 is dependent on
several factors, including: (1) AVDD and DVDD, the power
supply voltages; (2) IOUTFS, the full-scale current output; (3)
fCLOCK, the update rate; and (4) the reconstructed digital input
waveform. The power dissipation is directly proportional to the
analog supply current, IAVDD, and the digital supply current,
IDVDD. IAVDD is directly proportional to IOUTFS, as shown in
Figure 24, and is insensitive to fCLOCK.
Conversely, IDVDD is dependent on both the digital input wave-
form, fCLOCK, and digital supply DVDD. Figures 25 and 26
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note, how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
IOUTFS – mA
35
5
220
4
6
8
10
12
14
16
18
30
25
20
15
10
I AVDD
–
mA
Figure 24. IAVDD vs. IOUTFS
RATIO (fCLOCK/fOUT)
18
16
0
0.01
1
0.1
I DVDD
–
mA
8
6
4
2
12
10
14
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 25. IDVDD vs. Ratio @ DVDD = 5 V
RATIO (fCLOCK/fOUT)
8
0
0.01
1
0.1
I DVDD
–
mA
6
4
2
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 26. IDVDD vs. Ratio @ DVDD = 3 V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9754-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9754 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9754 - Bulk |
| AD9754-EBZ | 功能描述:BOARD EVAL FOR AD9754 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9755 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AD9755: 14-Bit. 300 MSPS High-Speed TxDAC+?D/A Converter Data Sheet (Rev. A. 1/03) |
| AD9755AST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14-BIT, 300 MSPS TXDAC+ D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:CONVERTOR DA ((NW)) |
| AD9755-AST | 制造商:Analog Devices 功能描述: |
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