參數(shù)資料
型號(hào): AD9750
廠商: Analog Devices, Inc.
英文描述: 10-Bit D/A Converter(100MSPS,10位D/A轉(zhuǎn)換器)
中文描述: 10位D / A轉(zhuǎn)換器(100MSPS時(shí),10位的D / A轉(zhuǎn)換器)
文件頁(yè)數(shù): 5/21頁(yè)
文件大?。?/td> 280K
代理商: AD9750
AD9750
–5–
REV. 0
PRELIMINARY
DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
μ
F capacitor.
Analog Supply Voltage (+2.7 V to +5.5 V).
Digital Common.
Digital Supply Voltage (+2.7 V to +5.5 V).
Clock Input. Data latched on positive edge of clock.
TECHNICAL
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9750
NC = NO CONNECT
(MSB) DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
NC
NC
CLOCK
DVDD
DCOM
NC
AVDD
ICOMP
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
2–9
10
11–14, 19, 25
15
DB9
DB8–DB1
DB0
NC
SLEEP
Most Significant Data Bit (MSB).
Data Bits 1–8.
Least Significant Data Bit (LSB).
No Internal Connection.
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated
if not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO
to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to
ACOM). Requires 0.1
μ
F capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
16
REFLO
17
REFIO
18
20
21
22
23
24
26
27
28
FS ADJ
ACOM
IOUTB
IOUTA
ICOMP
AVDD
DCOM
DVDD
CLOCK
相關(guān)PDF資料
PDF描述
AD9752* 12-Bit. 125 MSPS High Performance TxDAC D/A Converter
AD9752-EB 12-Bit, 125 MSPS High Performance TxDAC D/A Converter
AD9752AR 12-Bit, 125 MSPS High Performance TxDAC D/A Converter
AD9752ARU 12-Bit, 125 MSPS High Performance TxDAC D/A Converter
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