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| 型號： | AD9750-EB |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/22頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9750 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標準包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時間： | 35ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9750 |
| 相關(guān)產(chǎn)品： | AD9750ARZ-ND - IC DAC 10BIT 125MSPS 28-SOIC AD9750ARUZ-ND - IC DAC 10BIT 125MSPS 28TSSOP AD9750ARUZRL7-ND - IC DAC 10BIT 125MSPS 28TSSOP AD9750ARZRL-ND - IC DAC 10BIT 125MSPS 28SOIC |
AD9750
–4–
REV. 0
DIGITAL SPECIFICATIONS
Parameter
Min
Typ
Max
Units
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
1
3.5
5
V
Logic “1” Voltage @ DVDD = +3 V
2.1
3
V
Logic “0” Voltage @ DVDD = +5 V
1
0
1.3
V
Logic “0” Voltage @ DVDD = +3 V
0
0.9
V
Logic “1” Current
–10
+10
A
Logic “0” Current
–10
+10
A
Input Capacitance
5
pF
Input Setup Time (tS)
2.0
ns
Input Hold Time (tH)
1.5
ns
Latch Pulsewidth (tLPW)
3.5
ns
NOTES
1When DVDD = +5 V, and Logic 1 voltage
≈3.5 V and Logic 0 voltage ≈1.3 V, IVDD can increase by up to 10 mA depending on f
CLOCK.
Specifications subject to change without notice.
0.1%
tS
tH
tLPW
t
PD
t
ST
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
With
Parameter
Respect to
Min
Max
Units
AVDD
ACOM
–0.3
+6.5
V
DVDD
DCOM
–0.3
+6.5
V
ACOM
DCOM
–0.3
+0.3
V
AVDD
DVDD
–6.5
+6.5
V
CLOCK, SLEEP
DCOM
–0.3
DVDD + 0.3
V
Digital Inputs
DCOM
–0.3
DVDD + 0.3
V
IOUTA, IOUTB
ACOM
–1.0
AVDD + 0.3
V
ICOMP
ACOM
–0.3
AVDD + 0.3
V
REFIO, FSADJ
ACOM
–0.3
AVDD + 0.3
V
REFLO
ACOM
–0.3
+0.3
V
Junction Temperature
+150
°C
Storage Temperature
–65
+150
°C
Lead Temperature
(10 sec)
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
Temperature
Package
Model
Ranges
Descriptions
Options*
AD9750AR
–40
°C to +85°C 28-Lead 300 Mil SOIC R-28
AD9750ARU –40
°C to +85°C 28-Lead TSSOP
RU-28
AD9750-EB
Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 Mil SOIC
θ
JA = 71.4°C/W
θ
JC = 23°C/W
28-Lead TSSOP
θ
JA = 97.9°C/W
θ
JC = 14.0°C/W
(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9750 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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