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參數(shù)資料
| 型號： | AD9739A-FMC-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 58/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL W/FMC CONN FPGA DEV |
| 設(shè)計(jì)資源： | AD9739A-FMC-EBZ Gerber Files AD9739A-FMC-EBZ Layout |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.5G |
| 數(shù)據(jù)接口： | 串行，SPI? |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9739A |
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Data Sheet
AD9737A/AD9739A
Rev. | Page 61 of 64
Figure 187 shows a recommended lab setup that was used to
characterize the performance of the AD9737A/AD9739A. The
DPG2 is a dual port LVDS/CMOS data pattern generator that is
available from Analog Devices, Inc., with an up to 1.25 GSPS
data rate. The DPG2 directly interfaces to the AD9737A/AD9739A
evaluation board via Tyco Z-PACK HM-Zd connectors. A low
phase noise/jitter RF source such as an R&S SMA100A signal
generator is used for the DAC clock. A +5 V power supply is
used to power up the AD9737A/AD9739A evaluation board,
and SMA cabling is used to interface to the supply, clock source,
and spectrum analyzer. A USB 2.0 interface to a host PC is used
to communicate to both the AD9737A/AD9739A evaluation
board and the DPG2.
A high dynamic range spectrum analyzer is required to evaluate
the ac performance of the AD9737A/AD9739A reconstructed
waveform. This is especially the case when measuring ACLR
performance for high dynamic range applications such as
multicarrier DOCSIS CMTS applications. Harmonic, SFDR,
and IMD measurements pertaining to unmodulated carriers
can benefit by using a sufficiently high RF attenuation setting
because these artifacts are easy to identify above the spectrum
analyzer noise floor. However, reconstructed waveforms having
modulated carrier(s) often benefit from the use of a high dynamic
range RF amplifier and/or passive filters to measure close-in
and wideband ACLR performance when using spectrum
analyzers of limited dynamic range.
ADI PATTERN GENERATOR
DPG2
AD9739
EVAL. BOARD
RHODE AND
SCHWARTZ
SMA 100A
AGILENT PSA
E4440A
10 MHz
REFIN
10 MHz
REOUT
LAB
PC
USB 2.0
GPIB
LVDS
DATA
AND DCI
DCO
1.6GHz TO
2.5GHz
3dBm
POWER
SUPPLY
+5V
09616-
106
Figure 187. Lab Test Setup Used to Characterize the AD9737A/AD9739A
RECOMMENDED START-UP SEQUENCE
On power-up of the AD9737A/AD9739A, a host processor is
via its SPI port. Figure 188 shows a flowchart of the sequential
steps required. Table 29 provides more detail on the SPI register
write/read operations required to implement the flowchart
steps. Note the following:
A software reset is optional because the AD9737A/AD9739A
have both an internal POR circuit and a RESET pin.
The Mu controller must be first enabled (and in track mode)
before the data receiver controller is enabled because the DCO
output signal is derived from this circuitry.
A wait period is related to fDATA periods.
Limit the number of attempts to lock the controllers to three;
locks typically occur on the first attempt.
Hardware or software interrupts can be used to monitor the
status of the controllers.
CONFIGURE
SPI PORT
SOFTWARE
RESET
SET CLK
INPUT CMV
CONFIGURE
MU CONT.
WAIT A
FEW 100s
MU CONT.
LOCKED?
YES
NO
YES
WAIT A
FEW 100s
NO
RECONFIGURE
TXDAC FROM
DEFAULT SETTING
OPTIONAL
CONFIGURE
RX DATA
CONT.
RX DATA
CONT.
LOCKED?
09616-
107
Figure 188. Flowchart for Initialization and Configuration of the
C
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