VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I
參數(shù)資料
型號： AD9737A-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 45/64頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9737A
標準包裝： 1
系列： *
Data Sheet
AD9737A/AD9739A
Rev. | Page 5 of 64
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-
1996 reduced range link, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1
Input Common-Mode Voltage Range, VCOM
825
1575
mV
Logic High Differential Input Threshold, VIH_DTH
175
400
mV
Logic Low Differential Input Threshold, VIL_DTH
175
400
mV
Receiver Differential Input Impedance, RIN
80
120
Input Capacitance
1.2
pF
LVDS Input Rate
1250
MSPS
LVDS Minimum Data Valid Period (tMDE) (See Figure 159)
344
ps
LVDS CLOCK INPUT (DCI)2
Input Common-Mode Voltage Range, VCOM
825
1575
mV
Logic High Differential Input Threshold, VIH_DTH
175
400
mV
Logic Low Differential Input Threshold, VIL_DTH
175
400
mV
Receiver Differential Input Impedance, RIN
80
120
Input Capacitance
1.2
pF
Maximum Clock Rate
625
MHz
LVDS CLOCK OUTPUT (DCO)3
Output Voltage High (DCO_P or DCO_N)
1375
mV
Output Voltage Low (DCO_P or DCO_N)
1025
mV
Output Differential Voltage, |VOD|
150
200
250
mV
Output Offset Voltage, VOS
1150
1250
mV
Output Impedance, Single-Ended, RO
80
100
120
RO Single-Ended Mismatch
10
%
Maximum Clock Rate
625
MHz
1
DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.
2
DCI_P and DCI_N pins.
3
DCO_P and DCO_N pins with 100 differential termination.
C
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