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AD9714/AD9715/AD9716/AD9717
Rev. A | Page 7 of 80
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
DAC CLOCK INPUT (CLKIN)
VIH
2.1
3
V
VIL
0
0.9
V
Maximum Clock Rate
125
MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
25
MHz
Minimum Pulse Width High
20
ns
Minimum Pulse Width Low
20
ns
INPUT DATA
1.8 V Q Channel or DCLKIO Falling Edge
Setup
0.25
ns
Hold
1.2
ns
1.8 V I Channel or DCLKIO Rising Edge
Setup
0.13
ns
Hold
1.1
ns
3.3 V Q Channel or DCLKIO Falling Edge
Setup
0.2
ns
Hold
1.5
ns
3.3 V I Channel or DCLKIO Rising Edge
Setup
0.2
ns
Hold
1.6
ns
VIH
2.1
3
V
VIL
0
0.9
V