參數(shù)資料
型號(hào)： AD9716-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 44/80頁
文件大小： 0K
描述： ADC 12BIT DUAL 40LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 2
位數(shù)： 12
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9716
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 49 of 80
DIFFERENTIAL BUFFERED OUTPUT
USING AN OP AMP
A dual op amp (see the circuit shown in Figure 105) can be used
in a differential version of the single-ended buffer shown in
Figure 104. The same RC network is used to form a one-pole
differential, low-pass filter to isolate the op amp inputs from
the high frequency images produced by the DAC outputs. The
feedback resistors, RFB, determine the differential peak-to-peak
signal swing by the formula
VOUT = 2 × RFB × IFS
The maximum and minimum single-ended voltages out of the
amplifier are, respectively,
B
FB
REF
MAX
R
V
1
VMIN = VMAX RFB × IFS
The common-mode voltage of the differential output is
determined by the formula
VCM = VMAX RFB × IFS
07
26
5-
06
1
AD9714/AD9715/
AD9716/AD9717
IOUTP
IOUTN
RFB
VOUT
REFIO 34
28
RS
AVSS 25
CF
C
RFB
RB
CF
RS
RB
29
+
–
ADA4841-2
+
–
ADA4841-2
Figure 105. Single-Supply Differential Buffer
AUXILIARY DACs
The DACs of the AD9714/AD9715/AD9716/AD9717 feature
two versatile and independent 10-bit auxiliary DACs suitable
for dc offset correction and similar tasks.
Because the AUXDACs are driven through the SPI port, they
should never be used in timing-critical applications, such
as inside analog feedback loops.
To keep the pin count reasonable, these auxiliary DACs each
share a pin with the corresponding FSADJx resistor. They are,
therefore, usable only when enabled and when that DAC is
operated on its internal full-scale resistors. A simple I-to-V
converter is implemented on chip with selectable shunt resistors
(3.2 kΩ to 16 kΩ) such that if REFIO is set to exactly 1 V, REFIO/2
equals 0.5 V and the following equation describes the no load
output voltage:
k
16
5
.
1
V
5
.
0
S
DAC
OUT
R
I
V
Figure 106 illustrates the function of all the SPI bits controlling
these DACs with the exception of the QAUXEN (Register 0x0A,
Bit 7) and IAUXEN (Register 0x0C, Bit 7) bits and gating to
prohibit RS < 3.2 kΩ.
07
26
5-
0
43
+
–
OP AMP
AUXDAC
[9:0]
AVDD
RNG0
RNG1
REFIO
2
16k 16k
16k
4k
8k
OFS2
OFS1
OFS0
(OFS > 4 = 4)
AUX
PIN
RNG: 00 = > 125A
fS
01 = > 62A
fS
10 = > 31A
fS
11 = > 16A
fS
Figure 106. AUXDAC Simplified Circuit Diagram
The SPI speed limits the update rate of the auxiliary DACs. The
data is inverted such that IAUXDAC is full scale at 0x000 and zero
at 0x1FF, as shown in Figure 107.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
20
30
40
50
60 70
80
90 100
120 130
IAUXDAC (A)
OU
TP
U
T
(
V
)
07
26
5-
0
45
110
ROFFSET = 3.3k
ROFFSET = 4k
ROFFSET = 5.3k
ROFFSET = 8k
ROFFSET = 16k
OP AMP OUTPUT VOLTAGE vs. CHANGES
IN ROFFSET AND DAC CURRENT IN A
Figure 107. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V, No Load,
AUXDAC 0x1FF to 0x000
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