The power dissipation, PD
參數(shù)資料
型號： AD9705-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 31/44頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9705
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 175M
數(shù)據(jù)接口： 串行
設(shè)置時間： 11ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9705
相關(guān)產(chǎn)品： AD9705BCPZRL7-ND - IC DAC TX 10BIT 175MSPS 32-LFCSP
AD9705BCPZ-ND - IC DAC TX 10BIT 175MSPS 32-LFCSP
Data Sheet
AD9704/AD9705/AD9706/AD9707
Rev. B | Page 37 of 44
POWER DISSIPATION
The power dissipation, PD, of the AD9704/AD9705/AD9706/
AD9707 is dependent on several factors that include
The power supply voltages (AVDD, CLKVDD, and DVDD)
The full-scale current output, IOUTFS
The update rate, fCLOCK
The reconstructed digital input waveform
Power dissipation is directly proportional to the analog supply
current, IAVDD, and the digital supply current, IDVDD. IAVDD is equal to
a fixed current plus IOUTFS, as shown in Figure 80. IDVDD is proportional
to fCLOCK and increases with increasing analog output frequencies.
Figure 82 shows IDVDD as a function of full-scale sine wave output
ratios (fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
ICLKVDD is directly proportional to fCLOCK and is higher for differential
clock operation than for single-ended operation, as shown in
Figure 84. This difference in clock current is due primarily to the
differential clock receiver, which is disabled in single-ended
clock mode.
10
9
8
7
6
5
4
3
2
1
0
12
345
I AV
DD
(m
A
)
IOUTFS (mA)
0
592
6-
080
Figure 80. IAVDD vs. IOUTFS at AVDD = 3.3 V
0
1.00
1.25
1.50
1.75
2.00
I AVD
D
(m
A
)
IOUTFS (mA)
05
92
6-
1
02
1
3
2
4
5
6
Figure 81. IAVDD vs. IOUTFS at AVDD = 1.8 V
10
9
8
7
6
5
4
3
2
1
0
0.01
0.1
1
I DVD
D
(m
A
)
fOUT/fCLOCK
05
92
6-
0
81
fCLOCK = 75MSPS
fCLOCK = 25MSPS
fCLOCK = 10MSPS
fCLOCK = 125MSPS
fCLOCK = 175MSPS
Figure 82. IDVDD vs. fOUT/fCLOCK Ratio at DVDD = 3.3 V
2.5
0
0.01
0.1
1
I DV
D
(m
A
)
fOUT/fCLOCK
05
92
6-
0
98
0.5
1.0
1.5
2.0
2.5
fCLOCK = 80MSPS
fCLOCK = 10MSPS
fCLOCK = 25MSPS
fCLOCK = 50MSPS
Figure 83. IDVDD vs. fOUT/fCLOCK Ratio at DVDD = 1.8 V
5
4
3
2
1
0
100
50
150
200
I C
L
KV
DD
(m
A
)
fCLOCK (MSPS)
DIFF
SE
05
92
6-
0
82
Figure 84. ICLKVDD vs. fCLOCK at CLKVDD = 3.3 V
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