參數(shù)資料
型號(hào): AD9640ABCPZ-105
廠商: Analog Devices Inc
文件頁數(shù): 36/52頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 105MSPS 64LFCSP
設(shè)計(jì)資源: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 105M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 657mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,單極
AD9640
Rev. B | Page 41 of 52
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone, CMOS-
compatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Table 23. Mode Selection
Pin
External
Voltage
Configuration
SDIO/DCS
AVDD (default)
Duty cycle stabilizer enabled.
AGND
Duty cycle stabilizer disabled.
SCLK/DFS
AVDD
Twos complement enabled.
AGND (default)
Offset binary enabled.
SMI SDO/OEB
AVDD
Outputs in high impedance.
AGND (default)
Outputs enabled.
SMI SCLK/PDWN
AVDD
Chip in power-down or
standby.
AGND (default)
Normal operation.
SPI ACCESSIBLE FEATURES
A brief description of general features accessible via the SPI
follows. These features are described in detail in the AN-877
Application Note, Interfacing to High Speed ADCs via SPI. The
AD9640 part-specific features are described in detail following
Table 25, the external memory map register table.
Table 24. Features Accessible Using the SPI
Feature Name
Description
Modes
Allows user to set either power-down mode or
standby mode.
Clock
Allows user to access the DCS via the SPI.
Offset
Allows user to digitally adjust the converter
offset.
Test I/O
Allows user to set test modes to have known
data on output bits.
Output Mode
Allows user to set up outputs.
Output Phase
Allows user to set the output clock polarity.
Output Delay
Allows user to vary the DCO delay.
VREF
Allows user to set the reference voltage.
DON’T CARE
SDIO
SCLK
CSB
tS
tDH
tCLK
tDS
tH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
06547-
0
49
tLOW
tHIGH
Figure 73. Serial Port Interface Timing Diagram
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