參數(shù)資料
型號(hào)： AD9629-65EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION AD9629 65MSPS
設(shè)計(jì)資源： AD9649/29/09 Schematics
AD9649/29/09 Gerber Files
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 81.7mW @ 65MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9629
已供物品： 板
AD9629
Rev. 0 | Page 19 of 32
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9629. The VREF can be configured using either the internal
1.0 V reference or an externally applied 1.0 V reference voltage.
The various reference modes are summarized in the sections
that follow. The Reference Decoupling section describes the
best practices PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9629 detects the potential at the
SENSE pin and configures the reference into two possible modes,
which are summarized in Table 10. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 42), setting VREF to 1.0 V.
VREF
SENSE
0.5V
ADC
SELECT
LOGIC
0.1F
1.0F
VIN–
VIN+
ADC
CORE
08
54
0-
0
12
Figure 42. Internal Reference Configuration
If the internal reference of the AD9629 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 43 shows
how the internal reference voltage is affected by loading.
0
–3.0
02
LOAD CURRENT (mA)
RE
F
E
RE
NCE
V
O
L
T
AG
E
RR
O
R
(
%
)
.0
–0.5
–1.0
–1.5
–2.0
–2.5
0.2
0.4
0.6
0.8
1.0
1.4
1.6
1.8
1.2
INTERNAL VREF = 0.996V
08
54
0-
0
14
Figure 43. VREF Accuracy vs. Load Current
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 44 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
V
RE
F
E
RRO
R
(
m
V
)
VREF ERROR (mV)
0
85
40
-05
2
Figure 44. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 27). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
Table 10. Reference Configuration Summary
Selected Mode
SENSE Voltage (V)
Resulting VREF (V)
Resulting Differential Span (V p-p)
Fixed Internal Reference
AGND to 0.2
1.0 internal
2.0
Fixed External Reference
AVDD
1.0 applied to external VREF pin
2.0
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