參數(shù)資料
型號(hào): AD9629-40EBZ
廠商: Analog Devices Inc
文件頁數(shù): 29/32頁
文件大小: 0K
描述: BOARD EVALUATION AD9629 40MSPS
設(shè)計(jì)資源: AD9649/29/09 Schematics
AD9649/29/09 Gerber Files
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 40M
數(shù)據(jù)接口: 串行,SPI?
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 60.5mW @ 40MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9629
已供物品:
AD9629
Rev. 0 | Page 6 of 32
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = 1.0 dBFS, 50% duty
cycle clock, unless otherwise noted.
Table 3.
Parameter
Temp
AD9629-20/AD9629-40/AD9629-65/AD9629-80
Unit
Min
Typ
Max
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK)
Logic Compliance
CMOS/LVDS/LVPECL
Internal Common-Mode Bias
Full
0.9
V
Differential Input Voltage
Full
0.2
3.6
V p-p
Input Voltage Range
Full
GND 0.3
AVDD + 0.2
V
High Level Input Current
Full
10
+10
μA
Low Level Input Current
Full
10
+10
μA
Input Resistance
Full
8
10
12
Input Capacitance
Full
4
pF
LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)1
High Level Input Voltage
Full
1.2
DRVDD + 0.3
V
Low Level Input Voltage
Full
0
0.8
V
High Level Input Current
Full
50
75
μA
Low Level Input Current
Full
10
+10
μA
Input Resistance
Full
30
Input Capacitance
Full
2
pF
LOGIC INPUTS (CSB)2
High Level Input Voltage
Full
1.2
DRVDD + 0.3
V
Low Level Input Voltage
Full
0
0.8
V
High Level Input Current
Full
10
+10
μA
Low Level Input Current
Full
40
135
μA
Input Resistance
Full
26
Input Capacitance
Full
2
pF
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, IOH = 50 μA
Full
3.29
V
High Level Output Voltage, IOH = 0.5 mA
Full
3.25
V
Low Level Output Voltage, IOL = 1.6 mA
Full
0.2
V
Low Level Output Voltage, IOL = 50 μA
Full
0.05
V
DRVDD = 1.8 V
High Level Output Voltage, IOH = 50 μA
Full
1.79
V
High Level Output Voltage, IOH = 0.5 mA
Full
1.75
V
Low Level Output Voltage, IOL = 1.6 mA
Full
0.2
V
Low Level Output Voltage, IOL = 50 μA
Full
0.05
V
1 Internal 30 kΩ pull-down.
2 Internal 30 kΩ pull-up.
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