參數資料
型號： AD9627ABCPZ11-150
廠商： Analog Devices Inc
文件頁數： 20/72頁
文件大?。?/td> 0K
描述： IC ADC 11BIT 150MSPS 64LFCSP
標準包裝： 1
位數： 11
采樣率（每秒）： 150M
數據接口： 串行，SPI?
轉換器數目： 2
功率耗散（最大）： 890mW
電壓電源： 模擬和數字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數目和類型： 4 個單端，單極；2 個差分，單極
AD9627-11
Rev. B | Page 27 of 72
100
0.1F
50k
50k
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
CLK–
CLK+
ADC
AD9627-11
07054-
0
59
Figure 59. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK pin should be bypassed to ground with a 0.1 μF
capacitor in parallel with a 39 kΩ resistor (see Figure 60).
CLK+ can be driven directly from a CMOS gate. Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages of up to 3.6 V, making the selection
of the drive logic voltage very flexible.
OPTIONAL
100
0.1F
39k
50
1
150
RESISTOR IS OPTIONAL.
VCC
1k
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
CLK–
CLK+
ADC
AD9627-11
0
7054
-060
Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
150
RESISTOR IS OPTIONAL.
OPTIONAL
100
0.1F
VCC
50
1
1k
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
CLK–
CLK+
ADC
AD9627-11
0
705
4-
061
Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
Input Clock Divider
The AD9627-11 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
The AD9627-11 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized on every SYNC signal or only
on the first SYNC signal after the register is written. A valid
SYNC causes the clock divider to reset to its initial state. This
synchronization feature allows multiple parts to have their clock
dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9627-11 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the
performance of the AD9627-11. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 43.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered where the clock rate
can change dynamically. A wait time of 1.5 μs to 5 μs is required
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time period
that the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low
frequency SNR (SNRLF) at a given input frequency (fINPUT) due
to jitter (tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
)
10
/
(
LF
SNR
]
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 62.
07
05
4-
06
2
70
65
60
55
50
45
1
10
100
1000
SN
R
(
d
B
c
)
INPUT FREQUENCY (MHz)
3.00ps
0.05ps
0.20ps
0.5ps
1.0ps
1.50ps
2.00ps
2.50ps
MEASURED
Figure 62. SNR vs. Input Frequency and Jitter
OBSOLETE
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