參數(shù)資料
型號: AD9613-170EBZ
廠商: Analog Devices Inc
文件頁數(shù): 4/36頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9613-170
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 2
位數(shù): 12
采樣率(每秒): 170M
數(shù)據(jù)接口: 串行,SPI?
輸入范圍: 1.75 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 670mW @ 170MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9613
已供物品:
AD9613
Data Sheet
Rev. C | Page 12 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
09
63
7-
0
04
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D2–
D2+
DRV
DD
D3–
D3+
D4–
D4+
DCO
DC
O
+
D5–
D5+
DRV
DD
D6–
D6+
D7–
D7+
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AV
DD
AV
DD
VI
N
+
B
VI
N
–B
AV
DD
AV
DD
DNC
VC
M
DNC
AV
DD
AV
DD
VI
N
–A
VI
N
+
A
AV
DD
AV
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK+
CLK–
SYNC
DNC
DRVDD
DNC
D0– (LSB)
D0+ (LSB)
D1–
D1+
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
PDWN
OEB
CSB
SCLK
SDIO
OR+
OR–
D11+ (MSB)
D11– (MSB)
D10+
D10–
DRVDD
D9+
D9–
D8+
D8–
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9613
PARALLEL LVDS
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 4. Pin Configuration (Top View) for the LFCSP Interleaved Parallel LVDS Mode
Table 8. Pin Function Descriptions for the LFCSP Interleaved Parallel LVDS Mode
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
0
AGND,
Exposed Paddle
Ground
Analog Ground. The exposed thermal paddle on the bottom of the
package provides the analog ground for the part. This exposed paddle
must be connected to ground for proper operation.
4 to 9, 11, 12, 55, 56, 58
DNC
Do not connect. Do not connect to these pins.
10, 19, 28, 37
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54, 59, 60, 63, 64
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
ADC Analog
1
CLK+
Input
ADC Clock Input—True.
2
CLK
Input
ADC Clock Input—Complement.
51
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
52
VINA
Input
Differential Analog Input Pin () for Channel A.
57
VCM
Output
Common-Mode Level Bias Output for Analog Inputs. This pin should
be decoupled to ground using a 0.1 μF capacitor.
61
VINB
Input
Differential Analog Input Pin () for Channel B.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
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