參數(shù)資料
型號： AD9608BCPZRL7-105
廠商： Analog Devices Inc
文件頁數(shù)： 31/40頁
文件大小： 0K
描述： IC ADC 10BIT 105MSPS 64LFCSP
標準包裝： 750
位數(shù)： 10
采樣率（每秒）： 105M
數(shù)據(jù)接口： LVDS，并聯(lián)，串行，SPI
轉換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，2 個差分
AD9608
Rev. 0 | Page 37 of 40
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Power Modes (Register 0x08)
Bits[7:6]—Open
Bit 5—External Power-Down Pin Function
If set, the external PDWN pin initiates power-down mode.
If clear, the external PDWN pin initiates standby mode.
Bits[4:2]—Open
Bits[1:0]—Internal Power-Down Mode
In normal operation (Bits[1:0] = 00), both ADC channels are
active.
In power-down mode (Bits[1:0] = 01), the digital data path clocks
are disabled while the digital data path is reset. Outputs are
disabled.
In standby mode (Bits[1:0] = 10), the digital data path clocks
and the outputs are disabled.
During a digital reset (Bits[1:0] = 11), the digital data path clocks
are disabled while the digital data path is held in reset. The outputs
are enabled in this state. For optimum performance, it is recom-
mended that both ADC channels be reset simultaneously. This
is accomplished by ensuring that both channels are selected via
Register 0x05 prior to issuing the digital reset instruction.
Enhancement Control (Register 0x0C)
Bits[7:3]—Open
Bit 2—Chop Mode
For applications that are sensitive to offset voltages and other
low frequency noise, such as homodyne or direct-conversion
receivers, chopping in the first stage of the AD9628 is a feature
that can be enabled by setting Bit 2. In the frequency domain,
chopping translates offsets and other low frequency noise to
fCLK/2 where it can be filtered.
Bits[1:0]—Open
Output Mode (Register 0x14)
Bits[7:6]—Output Port Logic Type
00 = CMOS, 1.8 V
10 = LVDS, ANSI
11 = LVDS, reduced range
Bit 5—Output Interleave Enable
For LVDS outputs, setting Bit 5 enables interleaving. Channel A
is sent coincident with a high DCO clock, and Channel B is
coincident with a low DCO clock. Clearing Bit 5 disables the
interleaving feature. Channel A is sent on least significant bits
(LSBs), and Channel B is sent on most significant bits (MSBs).
The even bits are sent coincident with a high DCO clock, and
the odd bits are sent coincident with a low DCO clock.
For CMOS outputs, setting Bit 5 enables interleaving in CMOS
DDR mode. On ADC Output Port A, Channel A is sent coincident
with a low DCO clock, and Channel B is coincident with a high
DCO clock. On ADC Output Port B, Channel B is sent coincident
with a low DCO clock, and Channel A is coincident with a high
DCO clock. Clearing Bit 5 disables the interleaving feature, and
data is output in CMOS SDR mode. Channel A is sent to Port A,
and Channel B is sent to Port B.
Bit 4—Output Port Disable
Setting Bit 4 high disables the output port for the channels
selected in Bits[1:0] of the device index register (Register 0x05).
Bit 3—Open
Bit 2—Output Invert
Setting Bit 2 high inverts the output port data for the channels
selected in Bits[1:0] of the device index register (Register 0x05).
Bits[1:0]—Output Format
00 = offset binary
01 = twos complement
10 = Gray code
Sync Control (Register 0x3A)
Bits[7:3]—Open
Bit 2—Clock Divider Next Sync Only
If the clock divider sync enable bit (Address 0x3A, Bit 1) is high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable bit
resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high. This is continuous sync mode.
Bit 0—Open
Transfer (Register 0xFF)
All registers except Register 0x100 are updated the moment they
are written. Setting Bit 0 of this transfer register high initializes the
settings in the ADC sample rate override register (Address 0x100).
Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the device.
Any attempt to upgrade the default speed grade results in a chip
power-down. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is written high.
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