- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄9093 > AD9572ACPZPEC-RL (Analog Devices Inc)IC PLL CLOCK GEN 25MHZ 40LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9572ACPZPEC-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 40LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類(lèi)型： | 時(shí)鐘發(fā)生器，扇出配送，多路復(fù)用器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:7 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 156.25MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-WQ（6x6） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)
AD9572
Rev. B | Page 19 of 20
sine wave or square wave, provided that an external divider is
used to bias the input at VS/2.
Table 17. REFSEL (Pin 9) Definition
REFSEL
Reference Source
0
REFCLK input
1
Internal crystal oscillator
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as important
as the circuit design. Proper RF techniques must be used for
device selection, placement, and routing, as well as for power
supply bypassing and grounding to ensure optimum performance.
Each power supply pin should have independent decoupling and
connections to the power supply plane. It is recommended that the
device exposed paddle be directly connected to the ground plane
by a grid of at least nine vias. Care should be taken to ensure that
the output traces cannot couple onto the reference or crystal input
circuitry. Traces should not be routed under the crystal. Output
signal traces should be kept on the top PCB layer; these traces have
very high edge rates, and the use of PCB vias will result in signal
integrity problems.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-BTN-MV-S | CONVERTER MOD DC/DC 18.5V 150W |
| X9410WP24I-2.7 | IC XDCP DUAL 64-TAP 10K 24-DIP |
| X9410WP24I | IC XDCP DUAL 64-TAP 10K 24-DIP |
| D38999/20JD15JD | CONN RCPT 15POS WALL MNT W/SCKT |
| AD9571ACPZPEC-RL | IC PLL CLOCK GEN 25MHZ 40LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9572-EVALZ-LVD | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs |
| AD9572-EVALZ-PEC | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs |
| AD9572XCPZLVD | 制造商:Analog Devices 功能描述: |
| AD9572XCPZPEC | 制造商:Analog Devices 功能描述: |
| AD9573 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。