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參數(shù)資料
| 型號： | AD9549ABCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 61/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準包裝： | 750 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9549
Rev. D | Page 64 of 76
MONITOR (REGISTER 0x0300 TO REGISTER 0x0335)
Register 0x0300—Status
This register contains the status of the chip. This register is read-only and live update.
Table 74.
Bits
Bit Name
Description
7
Reserved
Reserved.
6
PFD frequency too high
This flag indicates that the frequency estimator failed and detected a PFD frequency that is too high.
This bit is relevant only if the user is relying on the frequency estimator to determine the input
frequency.
5
PFD frequency too low
This flag indicates that the frequency estimator failed and detected a PFD frequency that is too low.
This bit is relevant only if the user is relying on the frequency estimator to determine the input
frequency.
4
Frequency estimator done
True when the frequency estimator circuit has successfully estimated the input frequency. See the
Frequency Estimator section.
3
Reference selected
Reference selected.
0 = Reference A is active.
1 = Reference B is active.
2
Free run
DPLL is in holdover mode (free run).
1
Phase lock detect
This flag indicates that the phase lock detect circuit has detected phase lock. The amount of phase
adjustment is compared against a programmable threshold. Note that this bit can be set in single
tone and holdover modes and should be ignored in these cases.
0
Frequency lock detect
This flag indicates that the frequency lock detect circuit has detected frequency lock. This feature
compares the absolute value of the difference of two consecutive phase detector edges against a
programmable threshold. Because of this, frequency lock detect is more rigorous than phase lock
detect, and it is possible to have phase lock detect without frequency lock detect.
Register 0x0301—Status (Continued)
This register contains the status of the chip. This register is read-only and live update.
Table 75.
Bits
Bit Name
Description
7
Reserved
Reserved.
6
REFA valid
The reference validation circuit has successfully determined that Reference A is valid.
5
REFA LOR
A LOR (loss of reference) has occurred on Reference A.
4
REFA OOL
The OOL (out of limits) circuit has determined that Reference A is out of limits.
3
Reserved
Reserved.
2
REFB Valid
The reference validation circuit has successfully determined that Reference B is valid.
1
REFB LOR
A LOR (loss of reference) has occurred on Reference B.
0
REFB OOL
The OOL (out of limits) circuit has determined that Reference B is out of limits.
Register 0x0302 and Register 0x0303—IRQ Status
These registers contain the chip status (Registers 0x0300 and Register 0x0301) at the time of IRQ. These bits are cleared with an IRQ reset
(see Register 0x0012, Bit 5).
Register 0x0304—IRQ Mask
Table 76.
Bits
Bit Name
Description
[7:3]
Reserved
Reserved.
2
Reference changed
Trigger IRQ when active reference clock selection changes.
1
Leave free run
Trigger IRQ when DPLL leaves free-run (holdover) mode.
0
Enter free run
Trigger IRQ when DPLL enters free-run (holdover) mode.
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