- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9673 > AD9548BCPZ (Analog Devices Inc)IC CLOCK GEN/SYNCHRONIZR 88LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9548BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
AD9548
Data Sheet
Rev. E | Page 110 of 112
If x is an integer, then y = x. Otherwise, y is the nearest integer to
x. For example, round(2.1) = 2, round(2.5) = 3, and round(3.1) =
3.
The ceil() function
y = ceil(x)
If x is an integer, then y = x. Otherwise, y is the next integer to
the right on the number line. For example, ceil(2.8) = 3,
whereas ceil(2.8) = 2.
The min() function
y = min(x0, x1, ... xn)
where x0 through xn is a list of real numbers, and the value of y
is the number in the list that is the farthest to the left on the
number line.
The max() function
y = max(x0, x1, ... xn)
where x0 through xn is a list of real numbers, and the value of y
is the number in the list that is the farthest to the right on the
number line.
The log2() function
)
2
(
ln
)
(
ln
)
(
log
2
x
=
where ln() is the natural log function and x is a positive,
nonzero number.
Assume that the coefficient calculations for α, β, γ, and δ yield
the following results:
012735446
.
0
=
α
5
10
98672
.
6
×
=
β
5
10
50373
.
7
×
=
γ
002015399
.
0
=
δ
These values are floating point numbers that must be quantized
according to the bit widths of the linear and exponential
components of the coefficients as they appear in the register
map. Note that the calculations that follow indicate a positive
value for the register entries of β and γ. The reason is that β and
γ, which are supposed to be negative values, are stored in the
stored values to negative numbers within its signal processing
core. A detailed description of the register value computations
for α, β, γ, and δ is contained in the Calculation of the α
Register Values section to the Calculation of the δ Register
Values section.
CALCULATION OF THE α REGISTER VALUES
The quantized α coefficient consists of four components, α0, α1,
α2, and α3 according to
3
2
1
0
quantized
α
+
×
=
≈
16
2
where α0, α1, α2, and α3 are the register values. α2 provides
front-end gain and α3 provides back-end gain, and α1 shifts the
binary decimal point of α0 to the left to accommodate small
values of α. Calculation of α1 is a two-step process, as follows:
)
0
)),
(
(log
ceil
,
1
(
if
2 α
α
<
=
w
[
] )0
,
)
,
0
max(
,
63
min
,
1
(
if
1
w
<
=
α
If gain is necessary (that is, α > 1), then it is beneficial to apply
most or all of it to the front-end gain (α2) implying that the
calculation of α2 is to be done before α3. Calculation of α2 is a
three-step process that leads directly to the calculation of α3.
)
0
)),
(
(log
ceil
,
1
(
if
2 α
α >
=
x
[
] )0
,
)
,
0
max(
,
22
min
,
1
(
if
x
y
>
=
α
)
,
7
,
8
(
if
2
y
≥
=
α
)
0
,
7
,
8
(
if
3
≥
=
y
α
Calculation of α0 is a two-step process, as follows:
)
2
(
round
16
3
2
1
z
α
+
×
=
[
])
,
1
max(
,
535
,
65
min
z
0 =
α
Using the example value of α = 0.012735446 yields
w = 6, so α1 = 6
x = 0 and y = 0, so α2 = 0 and α3 = 0
z = 53,416.332099584, so α0 = 53,416
This leads to the following quantized value, which is very close
to the desired value of 0.012735446:
1
0127356682
.
0
2
53416
22
≈
×
=
quantized
α
CALCULATION OF THE β REGISTER VALUES
The quantized β coefficient consists of two components, β0 and
β1 according to
)
17
(
1
2
β
+
×
=
≈
0
quantized
where β0 and β1 are the register values. Calculation of β1 is a
two-step process that leads to the calculation of β0, which is also
a two-step process.
))
(
(log
ceil
2
β
=
x
[
])
,
0
max(
,
31
min
x
1 =
β
)
2
(
round
17
1
y
β
+
×
=
[
])
,
1
max(
,
071
,
131
min
y
0 =
β
Using the example value of β = 6.98672 × 105 yields
x = 13, so β1 = 13
y = 75,019.3347657728, so β0 = 75,019
This leads to the following quantized value, which is very close
to the desired value of 6.98672x105:
5
30
10
986688823
.
6
2
019
,
75
×
≈
×
=
quantized
β
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V375C36M150BL3 | CONVERTER MOD DC/DC 36V 150W |
| MAX3676EHJ+ | IC CLOCK RECOVERY 32-TQFP |
| ADN2813ACPZ | IC CLK/DATA REC 1.25GBPS 48LFCSP |
| AD800-52BRZ | IC CLK\DATA RECOVERY PLL 20SOIC |
| SY87700VZH | IC CLK/DATA RECOVERY 3.3V 28SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
| AD9549 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549/PCBZ | 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk |
| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。