參數(shù)資料
型號(hào)： AD9547/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 95/104頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9547
設(shè)計(jì)資源： AD9547 Schematic
AD9574 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9547
主要屬性： 2 個(gè)差分式或 4 個(gè)單端輸入
次要屬性： CMOS，LVPECL 和 LVDS 兼容
已供物品： 板
AD9547
Data Sheet
Rev. E | Page 90 of 104
Register0x0A03—Reset Functions
Table 122. Reset Functions1
Address
Bit
Bit Name
Description
0x0A03
7
Unused
Unused.
6
Clear LF
Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool).
5
Clear CCI
Setting this bit (default = 0) clears the CCI filter (intended as a debug tool).
4
Clear phase accumulator
Setting this bit (default = 0) clears DDS phase accumulator (not a recommendedaction).
3
Reset auto sync
Settingthis bit (default = 0) resets theautomatic synchronizationlogic (seeRegister0x0403).
2
Reset TW history
Setting this bit (default = 0) resets the tuning word history logic (part of holdover
functionality).
1
Reset all IRQs
Setting this bit (default = 0) clears the entire IRQ monitor register (Register 0x0D02 to
Register 0x0D09). It is the equivalent of setting all the bits of the IRQ clearing register
(Register 0x0A04 to Register 0x0A0B).
0
Reset watchdog
Settingthis bit (default = 0) resets thewatchdogtimer(seeRegister 0x0211to Register0x0212).
Ifthe timer timesout, it simply starts a new timingcycle. Ifthe timerhas not yet timedout,
it restarts at Time 0 without causinga timeout event. Continuously resettingthe watchdogtimer
at intervals less thanits timeout periodprevents thewatchdogtimerfrom generatinga timeout
event.
1
All bits in this register are autoclearing.
Register0x0A04to Register0x0A0B—IRQ Clearing
The IRQ clearing registers are identical in format to the IRQ monitor registers (Address 0x0D02 to Address 0x0D09). When set to Logic 1,
an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ
clearing register is an autoclearing register.
Table 123. IRQ Clearing for SYSCLK
Address
Bit
Bit Name
Description
0x0A04
[7:6]
Unused
Unused.
5
SYSCLK unlocked
Clears SYSCLK unlocked IRQ.
4
SYSCLK locked
Clears SYSCLK lockedIRQ.
[3:2]
Unused
Unused.
1
SYSCLK cal complete
Clears SYSCLK calibrationcomplete IRQ.
0
SYSCLK cal started
Clears SYSCLK calibrationstarted IRQ.
Table 124. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM
Address
Bit
Bit Name
Description
0x0A05
[7:4]
Unused
Unused.
3
Distributionsync
Clears distributionsync IRQ.
2
Watchdog timer
Clears watchdog timer IRQ.
1
EEPROM fault
Clears EEPROM fault IRQ.
0
EEPROM complete
Clears EEPROM complete IRQ.
Table 125. IRQ Clearing for the Digital PLL
Address
Bit
Bit Name
Description
0x0A06
7
Switching
Clears switching IRQ.
6
Closed
Clears closed IRQ.
5
Free run
Clears free-run IRQ.
4
Holdover
Clears holdover IRQ.
3
Frequency unlocked
Clears frequency unlocked IRQ.
2
Frequency locked
Clears frequency locked IRQ.
1
Phase unlocked
Clears phase unlocked IRQ.
0
Phase locked
Clears phase lockedIRQ.
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