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參數(shù)資料
| 型號(hào)： | AD9540-VCO/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL CLK GEN SYNTH 48LFCSP |
| 設(shè)計(jì)資源： | AD9540 Eval Brd Schematics AD9540 Eval Brd BOM AD9540 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 已用 IC / 零件： | AD9540 |
| 已供物品： | 板 |
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AD9540
Rev. A | Page 20 of 32
DDS AND DAC
Finally, the amplitude words are piped to a 10-bit DAC. Because
the DAC is a sampled data system, the output is a reconstructed
sine wave that needs to be filtered to take high frequency images
out of the spectrum. The DAC is a current steering DAC that is
AVDD referenced. To get a measurable voltage output, the DAC
outputs must be terminated through a load resistor to AVDD,
typically 50 . At positive full scale, IOUT sinks no current and
the voltage drop across the load resistor is 0. However, the IOUT
output sinks the programmed full-scale output current of the
DAC, causing the maximum output voltage drop across the load
resistor. At negative full-scale, the situation is reversed and IOUT
sinks the full-scale current (and generates the maximum drop
across the load resistor), while IOUT sinks no current (and
generates no voltage drop). At midscale, the outputs sink equal
amounts of current, generating equal voltage drops.
The precision frequency division within the device is
accomplished using DDS technology. The DDS can control the
digital phase relationships by clocking a 48-bit accumulator.
The incremental value loaded into the accumulator, known as
the frequency tuning word, controls the overflow rate of the
accumulator. Similar to a sine wave completing a 2π radian
revolution, the overflow of the accumulator is cyclical in nature
and generates a fundamental frequency according to
48
2
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( s
o
f
FTW
f
×
=
}
2
W
{0
47
≤
≤ FT
The instantaneous phase of the sine wave is therefore the output
of the phase accumulator block. This signal can be phase-offset
by programming an additive digital phase that is added to each
phase sample coming out of the accumulator.
These instantaneous phase values are then piped through a
phase-to-amplitude conversion (sometimes called an angle-to-
amplitude conversion or AAC) block. This algorithm follows a
COS(x) relationship, where x is the phase coming out of the
phase offset block, normalized to 2π.
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參數(shù)描述 |
|---|---|
| AD9542/PCBZ | |
| AD9542BCPZ | 功能描述:SYNCHRONIZER & ADAPTIVE CLOCK TR 制造商:analog devices inc. 系列:* 包裝:托盤 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:64-WFQFN 裸露焊盤 供應(yīng)商器件封裝:64-LFCSP（9x9） 標(biāo)準(zhǔn)包裝:1 |
| AD9542BCPZ-REEL7 | 功能描述:SYNCHRONIZER & ADAPTIVE CLOCK TR 制造商:analog devices inc. 系列:* 包裝:帶卷（TR） 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:64-WFQFN 裸露焊盤 供應(yīng)商器件封裝:64-LFCSP（9x9） 標(biāo)準(zhǔn)包裝:750 |
| AD9543/PCBZ | 功能描述:EVALUATION BOARD AD9543 制造商:analog devices inc. 系列:- 零件狀態(tài):在售 主要用途:計(jì)時(shí)，時(shí)鐘同步器 嵌入式:- 使用的 IC/零件:AD9543 主要屬性:- 輔助屬性:圖形用戶界面 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9543BCPZ | 功能描述:BBU DERIVATIVE FOR AD9545 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:時(shí)鐘同步器 PLL:是 輸入:差分或單端 輸出:CML、HCSL、LVDS 或單端 電路數(shù):2 比率 - 輸入:輸出:4：10 差分 - 輸入:輸出:是/是 頻率 - 最大值:2.4GHz 分頻器/倍頻器:是/無 電壓 - 電源:1.71 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:48-LFCSP（7x7） 標(biāo)準(zhǔn)包裝:1 |
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