參數(shù)資料
型號： AD9518-2ABCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 57/64頁
文件大?。?/td> 0K
描述： IC CLOCK GEN 6CH 2.2GHZ 48LFCSP
標準包裝： 1
類型： 時鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.33GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應商設備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
AD9518-2
Data Sheet
Rev. C | Page 60 of 64
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs (because they are open emitter) require
a dc termination to bias the output transistors. The simplified
equivalent circuit in Figure 43 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 53) or Y-termination (see Figure 54) is recommended.
In each case, the VS of the receiving buffer should match the
VS_LVPECL voltage. If it does not, ac coupling is recommended (see
Figure 55). In the case of Figure 55, pull-down resistors of <150
are not recommended when VS_LVPECL = 3.3 V; if used, damage to
the LVPECL drivers may result. The minimum recommended
pull-down resistor size for VS_LVPECL = 2.5 V is 100 .
The resistor network is designed to match the transmission line
impedance (50 ) and the switching threshold (VS 1.3 V).
VS_LVPECL
LVPECL
50
SINGLE-ENDED
(NOT COUPLED)
VS
VS_DRV
LVPECL
127
83
06431-
145
Figure 53. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
VS_LVPECL
LVPECL
Z0 = 50
VS = 3.3V
LVPECL
50
Z0 = 50
06431-
147
Figure 54. DC-Coupled 3.3 V LVPECL Y-Termination
VS_LVPECL
LVPECL
100 DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
VS
LVPECL
100
0.1nF
200
06431-
146
Figure 55. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 54, where VS_LVPECL = 2.5 V, the 50 termination
resistor that is connected to ground should be changed to 19 .
Thevenin-equivalent termination uses a resistor network to provide
50 termination to a dc voltage that is below VOL of the LVPECL
driver. In this case, VS_LVPECL on the AD9518 should equal VS of
the receiving buffer. Although the resistor combination shown
in Figure 54 results in a dc bias point of VS_LVPECL 2 V, the actual
common-mode voltage is VS_LVPECL 1.3 V because there is
additional current flowing from the AD9518 LVPECL driver
through the pull-down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that the pull-
down resistor is 62.5 , and the pull-up resistor is 250 .
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相關代理商/技術參數(shù)
參數(shù)描述
AD9518-2ABCPZ-RL7 功能描述:IC CLOCK GEN 6CH 2.2GHZ 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
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