- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1987 > AD9517-4ABCPZ-RL7 (Analog Devices Inc)IC CLOCK GEN 1.8GHZ VCO 48LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9517-4ABCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/80頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 1.8GHZ VCO 48LFCSP |
| 設(shè)計(jì)資源： | High Performance, Dual Channel IF Sampling Receiver (CN0140) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
AD9517-4
Data Sheet
Rev. E | Page 32 of 80
Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is less than 1600 MHz, a configuration that bypasses
the VCO divider can be used. This configuration differs from the
1600 MHz section only in that the VCO divider (divide-by-2,
divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed.
This limits the frequency of the clock source to <1600 MHz (due
to the maximum input frequency allowed at the channel dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
<1600 MHz, use the register settings that are shown in Table 25.
Table 25. Settings for Clock Distribution < 1600 MHz
Register
Function
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off)
0x1E1[0] = 1b
Bypass the VCO divider as source for
distribution section
0x1E1[1] = 0b
CLK selected as the source
When using the internal PLL with an external VCO of <1600 MHz,
the PLL must be turned on.
Table 26. Settings for Using Internal PLL with External VCO <
1600 MHz
Register
Function
0x1E1[0] = 1b
Bypass the VCO divider as source for
distribution section
0x010[1:0] = 00b
PLL normal operation (PLL on), along
with other appropriate PLL settings in
Register 0x010 to Register 0x01D
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the
VCO/VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 27. Setting the PFD Polarity
Register
Function
0x010[7] = 0b
PFD polarity positive (higher control voltage
produces higher frequency)
0x010[7] = 1b
PFD polarity negative (higher control
voltage produces lower frequency)
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9518-0ABCPZ | IC CLOCK GEN 6CH 2.8GHZ 48LFCSP |
| AD9518-1ABCPZ | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
| AD9518-2ABCPZ-RL7 | IC CLOCK GEN 6CH 2.2GHZ 48LFCSP |
| AD9518-3ABCPZ | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
| AD9518-4ABCPZ-RL7 | IC CLOCK GEN 6CH 1.8GHZ 48LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9517-4APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9517-4BCPZ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC CLOCK GENERATOR 1.8GHZ LFCSP-48 制造商:Analog Devices 功能描述:IC, CLOCK GENERATOR, 1.8GHZ, LFCSP-48, Clock IC Type:Clock Generator, Frequency: |
| AD9517-4BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9518-0 | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator |
| AD9518-0/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 6-Output Clock Generator With Integrated 2.8 GHZ VCO |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。