參數(shù)資料
型號(hào)： AD9516-4BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/80頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN 1.8GHZ VCO 64-LFCSP
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： 時(shí)鐘
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:14
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.8GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
配用： AD9516-4/PCBZ-ND - BOARD EVAL FOR AD9516-4 1.8GHZ
Data Sheet
AD9516-4
Rev. C | Page 27 of 80
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9516 can be configured in several ways. These
configurations must be set up by loading the control registers
or function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
High Frequency Clock Distribution—CLK or External
VCO > 1600 MHz
The AD9516 power-up default configuration has the PLL
powered off and the routing of the input set so that the
CLK/CLK input is connected to the distribution section
through the VCO divider (divide-by-2/ divide-by-3/divide-by-
4/divide-by-5/divide-by-6). This is a distribution only mode
that allows for an external input up to 2400 MHz (see Table 3).
The maximum frequency that can be applied to the channel
dividers is 1600 MHz; therefore, higher input frequencies must
be divided down before reaching the channel dividers. This
input routing can also be used for lower input frequencies, but
the minimum divide is 2 before the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency less than
2400 MHz. In this configuration, the internal VCO is not used,
and is powered off. The external VCO/VCXO feeds directly into
the prescaler.
The register settings shown in Table 21 are the default values of
these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers can also be set intentionally to
these values.
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Table 21. Default Settings of Some PLL Registers
Register
Function
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off).
0x1E0[2:0] = 010b
Set VCO divider = 4.
0x1E1[0] = 0b
Use the VCO divider.
0x1E1[1] = 0b
CLK selected as the source.
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 22. Settings When Using an External VCO
Register
Function
0x010[1:0] = 00b
PLL normal operation (PLL on).
0x010 to 0x01D
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP,
according to the intended loop configuration.
0x1E1[1] = 0b
CLK selected as the source.
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 23. Setting the PFD Polarity
Register
Function
0x010[7] = 0b
PFD polarity positive (higher control
voltage produces higher frequency).
0x010[7] = 1b
PFD polarity negative (higher control
voltage produces lower frequency).
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