參數(shù)資料
型號(hào)： AD9432BST-105
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 12-Bit, 80 MSPS/105 MSPS A/D Converter
中文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52
封裝： PLASTIC, LQFP-52
文件頁(yè)數(shù)： 2/16頁(yè)
文件大?。?/td> 431K
代理商： AD9432BST-105
REV. B
–2–
AD9432–SPECIFICATIONS
Test
Level
AD9432BST-80
Min
Typ
AD9432BST-105
Min
Typ
Parameter
Temp
Max
Max
Unit
RESOLUTION
12
12
Bits
DC ACCURACY
Differential Nonlinearity
+25
°
C
Full
+25
°
C
Full
Full
+25
°
C
Full
I
VI
I
VI
VI
I
V
–0.75
–1.0
–1.0
–1.5
Guaranteed
–3
±
0.25
±
0.5
±
0.5
±
1.0
+0.75
+1.0
+1.0
+1.5
–0.75
–1.0
–1.0
–1.5
±
0.25
±
0.5
±
0.5
±
1.0
+0.75
+1.0
+1.0
+1.5
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
Gain Error
1
Gain Tempco
1
Guaranteed
+2
150
+2
150
+7
–3
+7
% FS
ppm/
°
C
ANALOG INPUT
Input Voltage Range (AIN–
AIN)
Common-Mode Voltage
Input Offset Voltage
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
Full
Full
Full
Full
+25
°
C
+25
°
C
V
V
VI
VI
V
V
±
1.0
3.0
±
0
3
4
500
±
1.0
3.0
±
0
3
4
500
V
V
mV
k
pF
MHz
–5
2
+5
4
–5
2
+5
4
ANALOG REFERENCE
Output Voltage
Tempco
Input Bias Current
Full
Full
Full
VI
V
VI
2.4
2.5
50
15
2.6
2.4
2.5
50
15
2.6
V
ppm/
°
C
μΑ
50
50
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulsewidth High (t
EH
)
Encode Pulsewidth Low (t
EL
)
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
Output Valid Time (t
V
)
2
Output Propagation Delay (t
PD
)
2
Output Rise Time (t
R
)
2
Output Fall Time (t
F
)
Out-of-Range Recovery Time
Transient Response Time
Latency
Full
Full
+25
°
C
+25
°
C
+25
°
C
+25
°
C
Full
Full
Full
Full
+25
°
C
+25
°
C
Full
VI
IV
IV
IV
V
V
VI
VI
V
V
V
V
IV
80
105
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
Cycles
1
1
4.0
4.0
6.2
6.2
2.0
0.25
5.3
5.5
2.1
1.9
2
2
10
4.0
4.0
4.8
4.8
2.0
0.25
5.3
5.5
2.1
1.9
2
2
10
3.0
3.0
8.0
8.0
DIGITAL INPUTS
Encode Input Common Mode
Differential Input (ENC–
ENC
)
Single-Ended
Logic “1” Voltage
Logic “0” Voltage
Input Resistance
Input Capacitance
Full
Full
V
V
1.6
750
1.6
750
V
mV
Full
Full
Full
+25
°
C
IV
IV
VI
V
2.0
2.0
V
V
k
pF
0.8
8
0.8
8
3
5
4.5
3
5
4.5
DIGITAL OUTPUTS
Logic “1” Voltage (V
DD
= +3.3 V)
Logic “0” Voltage (V
DD
= +3.3 V)
Output Coding
Full
Full
VI
VI
V
DD
– 0.05
V
DD
– 0.05
V
V
0.05
0.05
Two’s Complement
Two’s Complement
POWER SUPPLY
Power Dissipation
3
Power Supply Rejection Ratio (PSRR) +25
°
C
I
VCC
I
VDD
Full
VI
I
VI
VI
790
0.5
158
9.5
1000
+5
200
12.2
850
0.5
170
12.5
1100
+5
220
16
mW
mV/V
mA
mA
–5
–5
Full
Full
(V
DD
= 3.3 V, V
CC
= 5.0 V; external reference; differential encode input, unless
otherwise noted)
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