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參數(shù)資料
| 型號(hào)： | AD9288 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit, 40/80/100 MSPS Dual A/D Converter |
| 中文描述： | 8位，40/80/100 MSPS雙通道的A / D轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 205K |
| 代理商： | AD9288 |
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REV. 0
AD9288
–4–
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
D
B
1
2
3
4
5
6
7
8
9
10
11
12
D
A
D
A
E
A
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
NC
NC
GND
V
DD
GND
V
D
V
D
GND
V
DD
E
B
G
V
D
(
B
D
B
GND
A
IN
A
A
IN
A
DFS
REF
IN
A
REF
OUT
REF
IN
B
NC = NO CONNECT
S1
S2
A
IN
B
A
IN
B
GND
GND
NC
NC
D
B
D
B
D
B
D
B
D
A
V
D
V
D
D
A
(
D
A
D
A
AD9288
G
D
A
D
A
D
B
V
D
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1, 12, 16, 27, 29,
32, 34, 45
2
3
GND
A
IN
A
A
IN
A
Ground.
Analog Input for Channel A.
Analog Input for Channel A
(Complementary).
Data Format Select: (Offset
binary output available if set
low. Twos complement output
available if set high).
Reference Voltage Input for
Channel A.
Internal Reference Voltage.
Reference Voltage Input for
Channel B.
User Select #1 (Refer to Table
I), Tied with Respect to V
D
.
User Select #2 (Refer to Table
I), Tied with Respect to V
D
.
Analog Input for Channel B
(Complementary).
Analog Input for Channel B.
Analog Supply (3 V).
Clock Input for Channel B.
Digital Supply (3 V).
Digital Output for Channel B.
Do Not Connect.
Digital Output for Channel A.
Clock Input for Channel A.
4
DFS
5
REF
IN
A
6
7
REF
OUT
REF
IN
B
8
S1
9
S2
10
A
IN
B
11
13, 30, 31, 48
14
15, 28, 33, 46
17–24
25, 26, 35, 36
37–44
47
A
IN
B
V
D
ENC
B
V
DD
D7
B
–D0
B
NC
D0
A
–D7
A
ENC
A
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the EN-
CODE pulse should be left in Logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” deter-
mined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE
and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product; re-
ported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Worst Harmonic
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9288/PCB | 制造商:Analog Devices 功能描述:8 BIT 40/80/100 MSPS DUAL ADC EVAL BOARD - Bulk |
| AD9288BST-100 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 100Msps 8-bit Parallel 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 8-BIT ADC |
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| AD9288BST-80 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 80Msps 8-bit Parallel 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:8 BIT 80 MSPS DUAL ADC - Bulk 制造商:Analog Devices 功能描述:IC 8-BIT ADC |
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