參數(shù)資料
型號： AD9269BCPZ-20
廠商： Analog Devices Inc
文件頁數(shù)： 3/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT SER 2CH 64LFCSP
特色產(chǎn)品： AD9269/65 Low-Power, High-Speed 16-Bit, 1.8V ADCs
標準包裝： 1
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 102mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極
AD9269
Rev. 0 | Page 11 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D12B
D13B
DR
VD
D
D14B
D1
5
B
(
M
S
B
)
OR
B
DCO
B
DCO
A
D0
A
(
L
S
B)
D1
A
D2
A
DR
VD
D
D3
A
D4
A
D5
A
D6
A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AV
D
AV
D
VI
N
+
B
VI
N
–
B
AV
D
AV
D
RB
IA
S
VC
M
SE
N
SE
VR
E
F
AV
D
AV
D
VI
N
–
A
VI
N
+
A
AV
D
AV
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK+
CLK–
SYNC
D0B (LSB)
D1B
D2B
D3B
D4B
D5B
DRVDD
D6B
D7B
D8B
D9B
D10B
D11B
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D15A (MSB)
D14A
D13A
D12A
D11A
DRVDD
D10A
D9A
D8A
D7A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9269
TOP VIEW
(Not to Scale)
08
53
8
-00
5
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
0, EP
AGND
The exposed paddle is the only ground connection. It must be soldered to the PCB analog ground to
ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.
1, 2
CLK+, CLK
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
3
SYNC
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
4 to 9, 11 to
18, 20, 21
D0B (LSB) to
D15B (MSB)
Channel B Digital Outputs. D0B is the LSB; D15B is the MSB.
10, 19, 28, 37
DRVDD
Digital Output Driver Supply (1.8 V to 3.3 V).
22
ORB
Channel B Out-of-Range Digital Output.
23
DCOB
Channel B Data Clock Digital Output.
24
DCOA
Channel A Data Clock Digital Output.
25 to 27, 29 to
36, 38 to 42
D0A (LSB) to
D15A (MSB)
Channel A Digital Outputs. D0A is the LSB; D15A is the MSB.
43
ORA
Channel A Out-of-Range Digital Output.
44
SDIO/DCS
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal
pull-up in non-SPI (DCS) mode.
45
SCLK/DFS
SPI Clock (SCLK). Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down.
DFS high: twos complement output.
DFS low: offset binary output.
46
CSB
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
47
OEB
Digital Input. 30 kΩ internal pull-down.
Low: enable Channel A and Channel B digital outputs.
High: three-state outputs.
48
PDWN
Digital Input. 30 kΩ internal pull-down.
High: power down device.
Low: run device, normal operation.
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