參數(shù)資料
型號： AD9253BCPZ-125
廠商： Analog Devices Inc
文件頁數(shù)： 20/40頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 125MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 540mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 4 個差分，雙極
Data Sheet
AD9253
Rev. 0 | Page 27 of 40
DIGITAL OUTPUTS AND TIMING
The AD9253 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 Ω termination at the receiver.
The AD9253 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be less than 24 inches and
that the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 70. Figure 71 shows
the LVDS output timing example in reduced range mode.
10
06
5-
07
4
D0 500mV/DIV
D1 500mV/DIV
DCO 500mV/DIV
FCO 500mV/DIV
4ns/DIV
Figure 70. AD9253-125, LVDS Output Timing Example in ANSI-644 Mode (Default)
10
06
5-
08
3
D0 400mV/DIV
D1 400mV/DIV
DCO 400mV/DIV
FCO 400mV/DIV
4ns/DIV
Figure 71. AD9253-125, LVDS Output Timing Example in Reduced Range Mode
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histo-
gram with trace lengths less than 24 inches on standard FR-4
material is shown in Figure 72.
6k
7k
1k
2k
3k
5k
4k
0
200ps
250ps
300ps
350ps
400ps
450ps
500ps
TI
E
J
ITTE
R
H
IS
T
OG
R
A
M
(
H
it
s)
500
400
300
200
100
–500
–400
–300
–200
–100
0
–0.8ns
–0.4ns
0ns
0.4ns
0.8ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(
m
V)
EYE: ALL BITS
ULS: 7000/400354
100
65-
0
75
Figure 72. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End
Termination Only
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