參數(shù)資料
型號(hào)： AD9252ABCPZ-50
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/52頁(yè)
文件大小： 0K
描述： IC ADC 14BIT SRL 50MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 50M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 773mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
輸入數(shù)目和類型： 16 個(gè)單端，單極；8 個(gè)差分，單極
Data Sheet
AD9252
Rev. E | Page 17 of 52
THEORY OF OPERATION
The AD9252 architecture consists of a pipelined ADC divided
into three sections: a 4-bit first stage followed by eight 1.5-bit
stages and a 3-bit flash. Each stage provides sufficient overlap
to correct for flash errors in the preceding stage. The quantized
outputs from each stage are combined into a final 14-bit result
in the digital correction logic. The pipelined architecture permits
the first stage to operate with a new input sample while the
remaining stages operate with preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9252 is a differential switched-
capacitor circuit designed for processing differential input signals.
This circuit can support a wide common-mode range while
maintaining excellent performance. An input common-mode
voltage of midsupply minimizes signal-dependent errors and
provides optimum performance.
S
H
CPAR
CSAMPLE
CPAR
VIN – x
H
S
H
VIN + x
H
06296-
017
Figure 33. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 33). When the input
circuit is switched into sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low-Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of low-Q
inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a shunt capacitor or two
single-ended capacitors can be placed on the inputs to provide a
matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, Frequency Domain Response of
Switched-Capacitor ADCs; the AN-827 Application Note, A
Resonant Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs; and the Analog Dialogue article “Transformer-Coupled
for more information. In general, the precise values depend on
the application.
The analog inputs of the AD9252 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
06296-
056
ANALOG INPUT COMMON-MODE VOLTAGE (V)
S
NR/
S
F
DR
(
d
B)
60
65
70
75
80
85
90
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
SNR (dB)
SFDR (dBc)
Figure 34. SNR/SFDR vs. Common-Mode Voltage,
fIN = 2.3 MHz, fSAMPLE = 50 MSPS
06296-
057
ANALOG INPUT COMMON-MODE VOLTAGE (V)
S
NR/
S
F
DR
(
d
B)
60
65
70
75
80
85
90
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
SNR (dB)
SFDR (dBc)
Figure 35. SNR/SFDR vs. Common-Mode Voltage,
fIN = 35 MHz, fSAMPLE = 50 MSPS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9252ABCPZ-50 制造商:Analog Devices 功能描述:IC, ADC, 14BIT, 50MSPS, LVDS, SERIAL
AD9252ABCPZRL7-50 功能描述:IC ADC 14BIT SRL 50MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD9252BCPZ-50 制造商:Analog Devices 功能描述:IC ((NW)) 制造商:Analog Devices 功能描述:IC,A/D CONVERTER,OCTAL,14-BIT,LLCC,64PIN
AD9252BCPZRL7-50 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 14-Bit, 50 MSPS Serial LVDS 1.8 V A/D Converter
AD9253 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
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