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參數(shù)資料
| 型號： | AD9248BCPZRL7-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| 中文描述： | DUAL 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC64 |
| 封裝： | 9 X 9 MM, MO-220VMMD, LFCSP-64 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 419K |
| 代理商： | AD9248BCPZRL7-40 |
AD9248
Preliminary Technical Data
Rev. PrE | Page 10 of 23
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60
55 54 53 52 51 50 49
59 58 57 56
PIN 1
IDENTIFIER
64-LEAD LF-CSP AND TQFP
TOP VIEW
(Not to Scale)
D4_A
D3_A
D2_A
D1_A
D0_A
DRVDD
DRGND
OTR_B
D11_B
D10_B
D9_B
D8_B
D
D
AD9248
AGND
VIN+_A
VIN–_A
AGND
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
AGND
VIN– _B
VIN+_B
AGND
AVDD
C
S
M
O
D
D
D
D
D
D
D6_A
D5_A
C
D
D
P
O
D
D
D
D
D
D
D
A
D
A
P
O
D
D
D
D13_B (MSB)
D12_B
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin
Number
2
VIN+_A
3
VIN–_A
15
VIN+_B
14
VIN- _B
6
REFT_A
7
REFB_A
11
REFT_B
10
REFB_B
8
VREF
9
SENSE
18
CLK_B
63
CLK_A
19
DCS
20
DFS
21
PDWN_B
60
PDWN_A
22
OEB_B
59
OEB_A
42–51, 54-
57
(MSB)
23–27, 30-
38
(MSB)
39
OTR_B
58
OTR_A
62
SHARED_REF
Mnemonic
Description
Analog Input Pin (+) for Channel A
Analog Input Pin (- ) for Channel A
Analog Input Pin (+) for Channel B
Analog Input Pin (- ) for Channel B
Differential Reference (+) for Channel A
Differential Reference (- ) for Channel A
Differential Reference (+) for Channel B
Differential Reference (- ) for Channel B
Voltage Reference Input/Output
Reference Mode Selection
Clock Input Pin for Channel B
Clock Input Pin for Channel A
Enable Duty Cycle Stabilizer (DCS) Mode
Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement)
Power-Down Function Selection for Channel B (Active High)
Power-Down Function Selection for Channel A (Active High)
Output Enable Bit for Channel B
Output Enable Bit for Channel A (Low Setting Enables Channel A Output Data Bus)
Channel A Data Output Bits
D0_A (LSB)-D13_A
D0_B (LSB) -D13_B
Channel B Data Output Bits
Out-of-Range Indicator for Channel B
Out-of-Range Indicator for Channel A
Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared
Reference Mode)
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| AD9248BCPZRL7-65 | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9248BCPZRL7-65 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BST-20 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BST-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BST-64 | 制造商:Analog Devices 功能描述:- Bulk |
| AD9248BST-65 | 制造商:Analog Devices 功能描述:ADC DUAL PIPELINED 65MSPS 14BIT PARALLEL 64LQFP - Bulk |
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