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參數(shù)資料
| 型號： | AD9248BCPZRL7-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| 中文描述： | DUAL 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC64 |
| 封裝： | 9 X 9 MM, MO-220VMMD, LFCSP-64 |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 419K |
| 代理商： | AD9248BCPZRL7-20 |
Preliminary Technical Data
AD9248
EQUIVALENT CIRCUITS
Rev. PrE | Page 15 of 23
Figure xx.
Equivalent Analog Input Circuit
Figure xx.
Equivalent Digital Output Circuit
Figure xx.
Equivalent Digital Input Circuit
THEORY OF OPERATION
The AD9248 consists of two high performance analog-to-
digital converters (ADCs) that are based on the AD9235
converter core. The dual ADC paths are independent, except for
a shared internal band gap reference source, VREF. Each of the
ADC’s paths consists of a proprietary front end sample-and-
hold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The pipelined ADC is divided into three
sections, consisting of a 4-bit first stage followed by eight 1.5-
bit stages and a final 3-bit fl ash. Each stage provides sufficient
overlap to correct for fl ash errors in the preceding stages. The
quantized outputs from each stage are combined through the
digital correction logic block into a final 12-bit result. The
pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on
preceding samples. Sampling occurs on the rising edge of the
respective clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution fl ash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the fl ash
ADC output to control a switched capacitor digital-to-analog
converter (DAC) of the same resolution. The DAC output is
subtracted from the stage’s input signal and the residual is
amplified (multiplied) to drive the next pipeline stage. The
residual multiplier stage is also called a multiplying DAC
(MDAC). One bit of redundancy is used in each one of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be
configured as ac- or dc-coupled in differential or single-ended
modes. The output-staging block aligns the data, carries out the
error correction, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
ANALOG INPUT
The analog input to the AD9248 is a differential switched
capacitor, SHA, that has been designed for optimum
performance while processing a differential input signal. The
SHA input accepts inputs over a wide common-mode range. An
input common-mode voltage of mid supply is recommended to
maintain optimal performance.
The SHA input is a differential switched capacitor circuit. In
Figure , the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network will create a low-pass filter at the ADC’s
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| AD9248BST-20 | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9248BCPZRL7-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BCPZRL7-65 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BST-20 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BST-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BST-64 | 制造商:Analog Devices 功能描述:- Bulk |
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