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參數(shù)資料
| 型號： | AD9245BCPZRL7-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 80 MSPS, 3 V A/D Converter |
| 中文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | EXPOSED PAD, MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 18/28頁 |
| 文件大小： | 1510K |
| 代理商： | AD9245BCPZRL7-80 |
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AD9245
03583-B-018
10
μ
F+
0.1
μ
F
VREF
SENSE
R2
R1
0.5V
AD9245
VIN–
VIN+
REFT
0.1
μ
F
0.1
μ
F
10
μ
F
0.1
μ
F
REFB
SELECT
LOGIC
ADC
CORE
+
Figure 35. Programmable Reference Configuration
EXTERNAL REFERENCE OPERATION
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. When multiple ADCs track one another, a single
reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. F
cal drift characteristics of the internal reference in both 1.0 V
and 0.5 V modes.
shows the typi-
igure 36
Figure 36. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 k load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.0 V.
TEMPERATURE (°C)
V
–40
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
80
70
60
50
40
30
20
10
0
–10
–20
–30
03583-B-040
VREF = 0.5V
VREF = 1.0V
OPERATIONAL MODE SELECTION
As discussed earlier, the AD9245 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock duty cycle stabilizer (DCS). The
MODE pin is a multilevel input that controls the data format
and DCS state. The input threshold values and corresponding
mode selections are outlined in
Table 9
Table 9. Mode Selection
MODE Voltage
Data Format
AVDD
Twos Complement
2/3 AVDD
Twos Complement
1/3 AVDD
Offset Binary
AGND (Default)
Offset Binary
.
Duty Cycle
Stabilizer
Disabled
Enabled
Enabled
Disabled
EVALUATION BOARD
The AD9245 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. Complete schematics and layout plots follow
and demonstrate the proper routing and grounding techniques
that should be applied at the system level.
It is critical that signal sources with very low phase noise (<1 ps
rms jitter) be used to realize the ultimate performance of the
converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.
The AD9245 can be driven single-ended or differentially
through a transformer. Separate power pins are provided to
isolate the DUT from the support circuitry. Each input configu-
ration can be selected by proper connection of various jumpers
(refer to the schematics).
An alternative differential analog input path using an AD8351
op amp is included in the layout, but is not populated in pro-
duction. Designers interested in evaluating the op amp with the
ADC should remove C15, R12, and R3, and populate the op
amp circuit. The passive network between the AD8351 outputs
and the AD9245 allows the user to optimize the frequency
response of the op amp for the application.
Rev. B | Page 18 of 28
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9245BCPZRL7-802 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter |
| AD9245BPCZ-80 | 制造商:Analog Devices 功能描述:14BIT 80MSPS - Bulk 制造商:Analog Devices 功能描述:Analog Devices AD9245BPCZ-80 Data Conversions |
| AD9245XCPZ-20 | 制造商:Analog Devices 功能描述:40 MSPS DUAL A/D CONVERTER - Bulk |
| AD9246 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter |
| AD9246-105EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter |
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