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參數(shù)資料
| 型號： | AD9245 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 80 MSPS, 3 V A/D Converter |
| 中文描述： | 14位，80MSPS的3V A/D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 1510K |
| 代理商： | AD9245 |
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AD9245
JITTER CONSIDERATIONS
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input fre-
quency (
f
INPUT
) due only to aperture jitter (
t
J
) can be calculated
with the following equation:
[
2
SNR
=
log
20
]
J
INPUT
t
f
×
π
In the equation, the rms aperture jitter represents the root-mean
square of all jitter sources, which include the clock input, analog
input signal, and ADC aperture jitter specification. IF undersam-
pling applications are particularly sensitive to jitter (see Figure 31).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9245. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other meth-
ods), it should be retimed by the original clock at the last step.
INPUT FREQUENCY (MHz)
S
1
40
75
70
65
60
55
50
45
1000
100
10
03583-B-041
0.2ps
MEASURED SNR
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
Figure 31. SNR vs. Input Frequency and Jitter
POWER DISSIPATION AND STANDBY MODE
As shown in
, the power dissipated by the AD9245 is
proportional to its sample rate. The digital power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The maximum DRVDD current
(
I
DRVDD
) can be calculated as
Figure 32
Figure 32. Power and Current vs. Sample Rate @ 2.5 MHz
Figure 32
N
f
C
V
I
CLK
LOAD
DRVDD
DRVDD
×
×
×
=
where
N
is the number of output bits, 14 in the case of the
AD9245. This maximum current occurs when every output bit
switches on every clock cycle, i.e., a full-scale square wave at the
Nyquist frequency,
f
CLK
/2. In practice, the DRVDD current will
be established by the average number of output bits switching,
which will be determined by the sample rate and the character-
istics of the analog input signal.
SAMPLE RATE (MSPS)
T
C
10
20
30
40
50
60
70
80
90
300
325
350
375
400
425
0
20
40
60
80
100
120
140
100
03583-B-035
ANALOG CURRENT
TOTAL POWER
DIGITAL CURRENT
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in
taken with the same operating conditions as the Typical Per-
formance Characteristics, and with a 5 pF load on each output
driver.
was
By asserting the PDWN pin high, the AD9245 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW if the CLK and analog inputs are static. During standby,
the output drivers are placed in a high impedance state.
Reasserting the PDWN pin low returns the AD9245 to its
normal operational mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB, it takes approximately 1 second to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
DIGITAL OUTPUTS
The AD9245 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to pro-
vide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads or
large fanouts may require external buffers or latches.
As detailed in
offset binary or twos complement.
, the data format can be selected for either
Table 9
Rev. B | Page 16 of 28
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9245BCP-80 | 14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9245BCPRL7-80 | 14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9245BCPZ-80 | 14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9245BCPZRL7-80 | 14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9248 | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9245BCP-20EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
| AD9245BCP-20EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9245 3 V A/D Converter,14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
| AD9245BCP-40EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
| AD9245BCP-40EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
| AD9245BCP-65EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9245 3V A/D CNVRTR,14BIT, 20 MSPS/40 MSPS/65 M - Bulk |
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