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參數(shù)資料
| 型號： | AD9241EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的14位，125 MSPS的單片機的A / D轉換器 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 495K |
| 代理商： | AD9241EB |
AD9241
REV. 0
–8–
converter. Specifically, the input to the
A/D core
is the difference
of the voltages applied at the VINA and VINB input pins.
Therefore, the equation,
V
CORE
= VINA – VINB
(1)
defines the output of the differential input stage and provides the
input to the A/D core.
The voltage,
V
CORE
, must satisfy the condition,
–
VREF
≤
V
CORE
≤
VREF
where
VREF
is the voltage at the
VREF
pin.
While an infinite combination of VINA and VINB inputs exist
to satisfy Equation 2, an additional limitation is placed on the
inputs by the power supply voltages of the AD9241. The power
supplies bound the valid operating range for VINA and VINB.
The condition,
AVSS –
0.3
V < VINA < AVDD +
0.3
V
(3)
AVSS
– 0.3
V
<
VINB
<
AVDD
+ 0.3
V
where
AVSS
is nominally 0 V and
AVDD
is nominally +5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both Equa-
tions 2 and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9241, see
Table IV.
Refer to Table I and Table II for a summary of the various
analog input and reference configurations
.
(2)
ANALOG INPUT OPERATION
Figure 21 shows the equivalent analog input of the AD9241,
which consists of a differential sample-and-hold amplifier
(SHA). The differential input structure of the SHA is highly
flexible, allowing the devices to be easily configured for either a
differential or single-ended input. The dc offset, or common-
mode voltage, of the input(s) can be set to accommodate either
single-supply or dual supply systems. Also, note that the analog
inputs, VINA and VINB, are interchangeable, with the exception
that reversing the inputs to the VINA and VINB pins results in a
polarity inversion.
C
S
Q
S1
Q
H1
VINA
VINB
C
S
Q
S1
C
PIN
–
C
PAR
C
PIN
+
C
PAR
Q
S2
C
H
Q
S2
C
H
Figure 21. Simplified Input Circuit
INTRODUCTION
The AD9241 uses a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last, consists of a low resolution flash A/D con-
nected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the differ-
ence between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash er-
rors. The last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers can be con-
figured to interface with +5 V or +3.3 V logic families.
The AD9241 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in the hold
mode. System disturbances just prior to the rising edge of the
clock and/or excessive clock jitter may cause the input SHA to
acquire the wrong value and should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 20, a simplified model of the AD9241, highlights the rela-
tionship between the analog inputs, VINA, VINB, and the
reference voltage, VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF defines
the maximum input voltage to the A/D
core. The minimum input
voltage to the A/D
core is automatically defined to be –VREF.
V
CORE
VINA
VINB
+VREF
–VREF
A/D
CORE
14
AD9241
Figure 20. Equivalent Functional Input Circuit
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config-
ure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
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