參數(shù)資料
型號(hào)： AD9241ASZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT 1.25MSPS 44-MQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 1.25M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 7
功率耗散（最大）： 85mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，單極；1 個(gè)差分，單極
產(chǎn)品目錄頁(yè)面： 780 (CN2011-ZH PDF)
AD9241
REV. 0
–9–
The input SHA of the AD9241 is optimized to meet the perfor-
mance requirements for some of the most demanding commu-
nication, imaging and data acquisition applications, while
maintaining low power dissipation. Figure 22 is a graph of the
full-power bandwidth of the AD9241, typically 40 MHz. Note
that the small signal bandwidth is the same as the full-power
bandwidth. The settling time response to a full-scale stepped
input is shown in Figure 23 and is typically less than 80 ns to
0.0025%. The low input referred noise of 0.36 LSB’s rms is
displayed via a grounded histogram and is shown in Figure 13.
FREQUENCY – MHz
AMPLITUDE
–
dB
2
0
–12
0.01
1.0
10.0
100
–2
–4
–6
–8
–10
0.1
Figure 22. Full-Power Bandwidth
SETTLING TIME – ns
CODE
16000
12000
0
60
10
20
30
40
50
8000
4000
70
80
Figure 23. Settling Time
The SHA’s optimum distortion performance for a differential or
single-ended input is achieved under the following two condi-
tions: (1) the common-mode voltage is centered around mid-
supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input
signal voltage span of the SHA is set at its lowest (i.e., 2 V input
span). This is due to the sampling switches, QS1, being CMOS
switches whose RON resistance is very low but has some signal
dependency causing frequency-dependent ac distortion while
the SHA is in the track mode. The RON resistance of a CMOS
switch is typically lowest at its midsupply, but increases sym-
metrically as the input signal approaches either AVDD or
AVSS. A lower input signal voltage span centered at midsupply
reduces the degree of RON modulation.
Figure 24 compares the AD9241’s THD vs. frequency perfor-
mance for a 2 V input span with a common-mode voltage of
1 V and 2.5 V. Note the difference in the amount of degrada-
tion in THD performance as the input frequency increases.
Similarly, note how the THD performance at lower frequencies
becomes less sensitive to the common-mode voltage. As the
input frequency approaches dc, the distortion will be domi-
nated by static nonlinearities such as INL and DNL. It is
important to note that these dc static nonlinearities are inde-
pendent of any RON modulation.
FREQUENCY – MHz
THD
–
dB
–40
–45
–85
–50
–75
–55
–60
–65
–70
–80
0.01
0.1
10.0
VCM = 1V
VCM = 2.5V
1.0
Figure 24. THD vs. Frequency for VCM = 2.5 V and 1.0 V
(AIN = –0.5 dB, Input Span = 2.0 V p-p)
Due to the high degree of symmetry within the SHA topology, a
significant improvement in distortion performance for differen-
tial input signals with frequencies up to and beyond Nyquist can
be realized. This inherent symmetry provides excellent cancella-
tion of both common-mode distortion and noise. In addition,
the required input signal voltage span is reduced by a factor of
two, which further reduces the degree of RON modulation and
its effects on distortion.
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 5 V input span) and matched
input impedance for VINA and VINB. Note that only a slight
degradation in dc linearity performance exists between the 2 V and
5 V input span as specified in AD9241 DC SPECIFICATIONS.
Referring to Figure 21, the differential SHA is implemented
using a switched-capacitor topology. Hence, its input imped-
ance and its subsequent effects on the input drive source should
be understood to maximize the converter’s performance. The
combination of the pin capacitance, CPIN, parasitic capacitance
CPAR, and the sampling capacitance, CS, is typically less than
16 pF. When the SHA goes into track mode, the input source
must charge or discharge the voltage stored on CS to the new
input voltage. This action of charging and discharging CS, which
is approximately 4 pF, averaged over a period of time and for a
given sampling frequency, FS, makes the input impedance ap-
pear to have a benign resistive component (i.e., 83 k
at F
S =
1.25 MSPS). However, if this action is analyzed within a sam-
pling period (i.e., T = <1/FS), the input impedance is dynamic
due to the instantaneous requirement of charging and discharg-
ing CS. A series resistor inserted between the input drive source
and the SHA input, as shown in Figure 25, provides effective
isolation.
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