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參數(shù)資料
| 型號： | AD9228ABCPZRL7-40 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SPI/SRL 40M 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 367mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，單極 |
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AD9228
Data Sheet
Rev. E | Page 22 of 56
For best dynamic performance, the source impedances driving
VIN + x and VIN x should be matched such that common-
mode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal
reference buffer creates the positive and negative reference
voltages, REFT and REFB, respectively, that define the span of
the ADC core. The output common-mode of the reference buffer
is set to midsupply, and the REFT and REFB voltages and span
are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD VREF)
Span = 2 × (REFT REFB) = 2 × VREF
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9228, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9228 either actively or
passively; however, optimum performance is achieved by driving
the analog input differentially. For example, using the AD8332
differential driver to drive the AD9228 provides excellent perfor-
mance and a flexible interface to the ADC (see Figure 51) for
baseband applications. This configuration is commonly used
for medical ultrasound systems.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 48 and Figure 49), because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9228.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
05
72
7-
0
08
2V p-p
R
*CDIFF
C
*CDIFF IS OPTIONAL
49.9
0.1μF
1k
AGND
AVDD
ADT1-1WT
1:1 Z RATIO
VIN – x
ADC
AD9228
VIN + x
C
Figure 48. Differential Transformer-Coupled Configuration
for Baseband Applications
ADC
AD9228
057
27-
047
2V p-p
2.2pF
1k
0.1μF
1k
AVDD
ADT1-1WT
1:1 Z RATIO
16nH
0.1μF
16nH
33
499
65
VIN + x
VIN – x
Figure 49. Differential Transformer-Coupled Configuration
for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the application requires a single-ended input configuration,
ensure that the source impedances on each input are well matched
in order to achieve the best possible performance. A full-scale
input of 2 V p-p can be applied to the ADC’s VIN + x pin while
the VIN x pin is terminated. Figure 50 details a typical single-
ended input configuration.
0
57
27
-00
9
2V p-p
R
49.9
0.1F
AVDD
1k 25
1k
AVDD
VIN – x
ADC
AD9228
VIN + x
*CDIFF
C
*CDIFF IS OPTIONAL
C
Figure 50. Single-Ended Input Configuration
AD8332
1k
187
0.1μF
1V p-p
0.1μF
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF
274
VIN – x
ADC
AD9228
VIN + x
05
72
7-
0
07
LPF
+
68pF
33
AVDD
680nH
10k
Figure 51. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter
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| AD9228ABCPZRL7-65 | 功能描述:IC ADC 12BIT SPI/SRL 65M 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9228BCPZ-40 | 制造商:Analog Devices 功能描述:ADC Quad Pipelined 40Msps 12-bit Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC SM 12-BIT ADC QUAD WAFFLE125 制造商:Analog Devices 功能描述:IC 12BIT ADC QUAD 40MSPS LFCSP48 制造商:Analog Devices 功能描述:IC, 12BIT ADC, QUAD 40MSPS, LFCSP48 |
| AD9228BCPZ-65 | 制造商:Analog Devices 功能描述:ADC Quad Pipelined 65Msps 12-bit Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC 12BIT ADC QUAD 65MSPS LFCSP48 |
| AD9228BCPZRL-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9228BCPZRL-65 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
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